Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of planes, and each of the planes includes a plurality of blocks. Each of the blocks includes a plurality of pages. The size of each page is N K-bytes, wherein N is a positive integer greater than 1. The controller is coupled to the flash memory to calculate the ECC bit number of each page using a detection unit of 1 Kbyte. The controller statistically calculates the number of detection units of the pages corresponding to different values of the ECC bit number in order to determine whether each plane of the flash memory is normal or not.

Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of planes, and each of the planes includes a plurality of blocks. Each of the blocks includes a plurality of pages. The size of each page is N K-bytes, wherein N is a positive integer greater than 1. The controller is coupled to the flash memory to calculate the ECC bit number of each page using a detection unit of 1 Kbyte. The controller statistically calculates the number of detection units of the pages corresponding to different values of the ECC bit number in order to determine whether each plane of the flash memory is normal or not.

Abstract: A transceiver with wake up detection includes a primary control unit, a transmission unit and a receiving unit, the transmission unit comprises a first logic set, a second logic set, a third logic set, a first loop, and a second loop. The first loop outputs a first differential signal, and the second loop outputs a second differential signal. The receiving unit comprises a wake up detection circuit having a first comparator, a second comparator and a fourth logic set. When the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic set outputs an idle state signal and a data signal to the primary control unit to make an operation mode of the transceiver switched from a low power mode to a normal mode.

Abstract: A transceiver with wake up detection includes a primary control unit, a transmission unit and a receiving unit, the transmission unit comprises a first logic set, a second logic set, a third logic set, a first loop, and a second loop. The first loop outputs a first differential signal, and the second loop outputs a second differential signal. The receiving unit comprises a wake up detection circuit having a first comparator, a second comparator and a fourth logic set. When the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic set outputs an idle state signal and a data signal to the primary control unit to make an operation mode of the transceiver switched from a low power mode to a normal mode.