Abstract: A semiconductor device having a contact plug is manufactured. The semiconductor device includes a substrate having a cell array region and a peripheral circuit region, a gate electrode on the substrate, and an interlayer dielectric layer on the substrate. The interlayer dielectric layer has an upper surface having a first height. The device further comprises a contact hole extending through the interlayer dielectric layer and a contact plug having an upper surface and electrically connecting to the substrate in the contact hole. The upper surface of the contact plug has a second height lower than the first height. A spacer is on the sidewall of the contact hole. A first conductive line is on the spacer and the upper surface of the contact plug.

Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

Abstract: A method of fabricating a semiconductor device, including forming contact pads in a first insulating layer on a substrate, forming a second insulating layer on the first insulating layer and on the contact pads, forming bit lines on the second insulating layer, the bit lines connected to a first plurality of the contact pads by bit line contact plugs, forming expanded contact holes in the second insulating layer between the bit lines, wherein the expanded contact holes are expanded toward the bit lines, and forming contact spacers on side walls of the expanded contact holes.

Abstract: A method of forming a tungsten pattern includes forming a preliminary tungsten pattern on a substrate and partially removing a surface of the preliminary tungsten pattern using deionized water to form the tungsten pattern.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

Abstract: In a semiconductor device capable of reducing an electromigration occurring in multilevel interconnections of a high-speed integrated circuit and a method of manufacturing the same, a contact stud is composed of a first portion penetrating an intermetal insulating film and a second portion protruding above the intermetal insulating film. The second portion has vertical sidewalls that are extended vertically with respect to the main surface of the semiconductor substrate and an upper surface that is extended parallel to the main surface. The vertical sidewalls and upper surface are entirely covered with the second metal interconnection layer. Also, in the method of fabricating a semiconductor device including multilevel interconnections, a hard mask pattern is formed on an intermetal insulating film. Then, a via hole is formed to penetrate the intermetal insulating film by etching a portion of the exposed intermetal insulating film.

Abstract: A bonding pad structure in an integrated circuit (IC) and a method for manufacturing thereof comprises a plurality of dummy patterns deposited in sub-layers of the IC, each dummy pattern being connected via a metal link to a plurality of complementary top surface bonding pads, wherein the dummy patterns and the metal link are constructed during the same process steps used to construct the circuit elements included in the IC, without additional or special process steps. Such an imbedded and anchored bonding pad provides contact reliability for both conductive and non-conductive pads used for the interconnection of integrated circuits in a manner that resists layer separation or de-lamination under pulling stresses that are present on the bonding pads.

Abstract: A bonding pad structure in an integrated circuit (IC) and a method for manufacturing thereof comprises a plurality of dummy patterns deposited in sub-layers of the IC, each dummy pattern being connected via a metal link to a plurality of complementary top surface bonding pads, wherein the dummy patterns and the metal link are constructed during the same process steps used to construct the circuit elements included in the IC, without additional or special process steps. Such an imbedded and anchored bonding pad provides contact reliability for both conductive and non-conductive pads used for the interconnection of integrated circuits in a manner that resists layer separation or de-lamination under pulling stresses that are present on the bonding pads.

Abstract: In a semiconductor device capable of reducing an electromigration occurring in multilevel interconnections of a high-speed integrated circuit and a method of manufacturing the same, a contact stud is composed of a first portion penetrating an intermetal insulating film and a second portion protruding above the intermetal insulating film. The second portion has vertical sidewalls that are extended vertically with respect to the main surface of the semiconductor substrate and an upper surface that is extended parallel to the main surface. The vertical sidewalls and upper surface are entirely covered with the second metal interconnection layer. Also, in the method of fabricating a semiconductor device including multilevel interconnections, a hard mask pattern is formed on an intermetal insulating film. Then, a via hole is formed to penetrate the intermetal insulating film by etching a portion of the exposed intermetal insulating film.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

Abstract: In a semiconductor device capable of reducing an electromigration occurring in multilevel interconnections of a high-speed integrated circuit and a method of manufacturing the same, a contact stud is composed of a first portion penetrating an intermetal insulating film and a second portion protruding above the intermetal insulating film. The second portion has vertical sidewalls that are extended vertically with respect to the main surface of the semiconductor substrate and an upper surface that is extended parallel to the main surface. The vertical sidewalls and upper surface are entirely covered with the second metal interconnection layer. Also, in the method of fabricating a semiconductor device including multilevel interconnections, a hard mask pattern is formed on an intermetal insulating film. Then, a via hole is formed to penetrate the intermetal insulating film by etching a portion of the exposed intermetal insulating film.

Abstract: A bonding pad structure in an integrated circuit (IC) and a method for manufacturing thereof comprises a plurality of dummy patterns deposited in sub-layers of the IC, each dummy pattern being connected via a metal link to a plurality of complementary top surface bonding pads, wherein the dummy patterns and the metal link are constructed during the same process steps used to construct the circuit elements included in the IC, without additional or special process steps. Such an imbedded and anchored bonding pad provides contact reliability for both conductive and non-conductive pads used for the interconnection of integrated circuits in a manner that resists layer separation or de-lamination under pulling stresses that are present on the bonding pads.

Abstract: A bonding pad structure in an integrated circuit (IC) and a method for manufacturing thereof comprises a plurality of dummy patterns deposited in sub-layers of the IC, each dummy pattern being connected via a metal link to a plurality of complementary top surface bonding pads, wherein the dummy patterns and the metal link are constructed during the same process steps used to construct the circuit elements included in the IC, without additional or special process steps. Such an imbedded and anchored bonding pad provides contact reliability for both conductive and non-conductive pads used for the interconnection of integrated circuits in a manner that resists layer separation or de-lamination under pulling stresses that are present on the bonding pads.

Abstract: A semiconductor memory device and a fabrication method thereof are provided. A plurality of gate electrode patterns is formed on a semiconductor substrate having isolation regions. Spacers are formed on sidewalls of the gate electrode patterns. A disposable pattern is formed on contact window area. An intermediate insulating pattern is formed except on the contact window area. The disposable pattern is removed to define a contact window. A contact node pattern is formed in the contact window.

Abstract: In a semiconductor device capable of reducing an electromigration occurring in multilevel interconnections of a high-speed integrated circuit and a method of manufacturing the same, a contact stud is composed of a first portion penetrating an intermetal insulating film and a second portion protruding above the intermetal insulating film. The second portion has vertical sidewalls that are extended vertically with respect to the main surface of the semiconductor substrate and an upper surface that is extended parallel to the main surface. The vertical sidewalls and upper surface are entirely covered with the second metal interconnection layer. Also, in the method of fabricating a semiconductor device including multilevel interconnections, a hard mask pattern is formed on an intermetal insulating film. Then, a via hole is formed to penetrate the intermetal insulating film by etching a portion of the exposed intermetal insulating film.

Abstract: A metal contact structure of a semiconductor device and a method for forming the same are provided. The diameter of the upper portion of a contact hole that exposes a region of a lower conductive layer is formed to be larger than the diameter of the lower portion of the contact hole. The metal contact structure is formed without a void or a key hole. This is accomplished by forming at least two metal layers to fill the contact hole by performing a first deposition, an etch back, and a second deposition. The metal layer which fills the contact hole is etched back using a barrier metal layer formed on the entire surface of the contact hole as an etching stop layer. Thus, a void or key hole is not generated by making the upper portion of the contact hole to be wider than the lower portion of the contact hole and by depositing the metal which fills the contact hole through the processes of firstly depositing the metal, etching back the metal, and secondly depositing the metal.