Patents by Inventor Tai Hirakawa

Tai Hirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11943822
    Abstract: A communication device is configured to wirelessly connect to an electronic apparatus. The communication device comprises a first communication unit and a second communication unit of a same type as that of the first communication unit and a control unit configured to control the first communication unit and the second communication unit. The control unit is configured to acquire a communication situation of the first communication unit with electronic apparatus and another communication situation of the second communication unit with electronic apparatus. The control unit is configured to execute an allocation process for determining a connection destination of an electronic apparatus to the first communication unit or the second communication unit based on the communication situations.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 26, 2024
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Yoshiyuki Imada, Masashi Kamata, Tai Hirakawa
  • Patent number: 11849352
    Abstract: A communication device includes a first communication unit and a second communication unit and is configured to wirelessly connect to an electronic apparatus. The first communication unit and the second communication unit operate in the same communication protocol. The first communication unit is configured to wait for a connection request from the electronic apparatus, and the second communication unit is configured to wirelessly connect to the electronic apparatus from which the first communication unit received a connection request. The first communication unit is configured to wait, where the first communication unit is not connected to the electronic apparatus, for a connection request in a first mode in which a waiting time period is relatively long, and the first communication unit is configured to wait, where the first communication unit is connected to the electronic apparatus, for a connection request in a second mode in which the waiting time period is relatively short.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 19, 2023
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Tai Hirakawa, Yoshiyuki Imada, Masashi Kamata
  • Patent number: 11606114
    Abstract: A communication device comprises a first communication unit that performs switching between transmission operation and reception operation in response to a value of a given bit of a clock, and a second communication unit of a same type as that of the first communication unit. In the communication device, a value of the given bit of the clock of the first communication unit and a value of the given bit of the clock of the second communication unit are synchronized with each other.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 14, 2023
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Tai Hirakawa, Yoshiyuki Imada, Masashi Kamata
  • Patent number: 11510255
    Abstract: A communication device comprises a first communication unit and a second communication unit of a same type as that of the first communication unit. The first communication unit or the second communication unit is configured to transmit, after wireless connection to an electronic apparatus is established, a waiting instruction signal for instructing the electronic apparatus to enter a state in which the electronic apparatus waits for a connection request.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: November 22, 2022
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Yoshiyuki Imada, Masashi Kamata, Tai Hirakawa
  • Publication number: 20220095407
    Abstract: A communication device is configured to wirelessly connect to an external apparatus. The communication device comprises a first communication unit and a control unit configured to control the first communication unit. The first communication unit is configured to operate as one of a master and a slave. When the first communication unit is connected to a given external apparatus, the control unit is configured to control a period during which the first communication unit operates as the slave in response to a communication situation of the first communication unit with a different external apparatus from the given external apparatus.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 24, 2022
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Tai Hirakawa, Yoshiyuki Imada, Masashi Kamata
  • Publication number: 20210410009
    Abstract: A communication device includes a first communication unit and a second communication unit and is configured to wirelessly connect to an electronic apparatus. The first communication unit and the second communication unit operate in the same communication protocol. The first communication unit is configured to wait for a connection request from the electronic apparatus, and the second communication unit is configured to wirelessly connect to the electronic apparatus from which the first communication unit received a connection request. The first communication unit is configured to wait, where the first communication unit is not connected to the electronic apparatus, for a connection request in a first mode in which a waiting time period is relatively long, and the first communication unit is configured to wait, where the first communication unit is connected to the electronic apparatus, for a connection request in a second mode in which the waiting time period is relatively short.
    Type: Application
    Filed: November 8, 2019
    Publication date: December 30, 2021
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Tai Hirakawa, Yoshiyuki Imada, Masashi Kamata
  • Publication number: 20210410202
    Abstract: A communication device is configured to wirelessly connect to an electronic apparatus. The communication device comprises a first communication unit and a second communication unit of a same type as that of the first communication unit and a control unit configured to control the first communication unit and the second communication unit. The control unit is configured to acquire a communication situation of the first communication unit with electronic apparatus and another communication situation of the second communication unit with electronic apparatus. The control unit is configured to execute an allocation process for determining a connection destination of an electronic apparatus to the first communication unit or the second communication unit based on the communication situations.
    Type: Application
    Filed: November 8, 2019
    Publication date: December 30, 2021
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Yoshiyuki Imada, Masashi Kamata, Tai Hirakawa
  • Publication number: 20210410203
    Abstract: A communication device comprises a first communication unit and a second communication unit of a same type as that of the first communication unit. The first communication unit or the second communication unit is configured to transmit, after wireless connection to an electronic apparatus is established, a waiting instruction signal for instructing the electronic apparatus to enter a state in which the electronic apparatus waits for a connection request.
    Type: Application
    Filed: November 8, 2019
    Publication date: December 30, 2021
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Yoshiyuki Imada, Masashi Kamata, Tai Hirakawa
  • Publication number: 20210399759
    Abstract: A communication device comprises a first communication unit that performs switching between transmission operation and reception operation in response to a value of a given bit of a clock, and a second communication unit of a same type as that of the first communication unit. In the communication device, a value of the given bit of the clock of the first communication unit and a value of the given bit of the clock of the second communication unit are synchronized with each other.
    Type: Application
    Filed: November 8, 2019
    Publication date: December 23, 2021
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Tai Hirakawa, Yoshiyuki Imada, Masashi Kamata
  • Patent number: 9042282
    Abstract: A first communication control unit and a second communication control unit share a single transmission and reception unit. The second communication control unit maintains connection with a terminal device while the first communication control unit is scanning frequency channels to search for an access point. When a search processing unit 104 detects an access point, the second communication control unit 200 switches the frequency channel for use in communication with the terminal device to the channel used in the detected access point.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 26, 2015
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventors: Tai Hirakawa, Hideaki Shimizu, Jun Nishihara, Kenji Inose
  • Patent number: 7694077
    Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: April 6, 2010
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
  • Publication number: 20080222360
    Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
    Type: Application
    Filed: February 20, 2008
    Publication date: September 11, 2008
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Tetsuo Hironaka, Hans Jurgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
  • Patent number: 7360024
    Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: April 15, 2008
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
  • Publication number: 20040088489
    Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
    Type: Application
    Filed: October 15, 2003
    Publication date: May 6, 2004
    Applicant: Semiconductor Technology Academic Research Center
    Inventors: Tetsuo Hironaka, Hans Jurgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi