Patents by Inventor Tai-I Wu

Tai-I Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085803
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: D724134
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 10, 2015
    Assignee: T-Link PPE Ltd
    Inventor: Tai-I Wu
  • Patent number: D757156
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 24, 2016
    Inventor: Tai-I Wu
  • Patent number: D757845
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 31, 2016
    Inventor: Tai-I Wu