Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: A memory device includes a command encoder encoding a command into a command code, a command decoder decoding the command code, selecting one of a plurality of read only memory (ROM) lines according to a decoding result, and outputting an enable signal through a selected ROM line among the plurality of ROM lines, a ROM code generator including a plurality of registers storing ROM codes for executing various operations and outputting a ROM code stored in a register to which the enable signal is input, among the plurality of registers, and an operation controller executing an algorithm according to the ROM code output from the ROM code generator.

Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device, which have an improved processing speed for a suspend operation. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to perform a data operation corresponding to an externally provided command on the memory cell array and a control circuit configured to control the peripheral circuit to perform the data operation by sequentially executing instructions corresponding to a plurality of instruction lines of an operation algorithm for the data operation and, when a suspend command is provided during the data operation, to perform a preset suspend operation in any one of a checker mode and an instant mode.

Abstract: The semiconductor memory device includes: a memory unit including a plurality of memory blocks; a decoder suitable for storing bad block information about the plurality of memory blocks, and outputting the bad block information in response to an address signal; and a control logic suitable for controlling the memory unit and the decoder to update a status register (SR) code in response to the bad block information when the semiconductor memory device at a ready state enters a busy state, and to perform a general operation according to the updated SR code and a command.

Abstract: Provided herein is a memory device including a memory cell array, a peripheral circuit configured to perform a first operation for the memory cell array, and a control circuit configured to generate an operation status code and output the operation status code. The first operation includes a plurality of second operations that are successively performed. The operation status code indicates, among the plurality of second operations, a current operation that is being performed by the peripheral circuit.

Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device, which have an improved processing speed for a suspend operation. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to perform a data operation corresponding to an externally provided command on the memory cell array and a control circuit configured to control the peripheral circuit to perform the data operation by sequentially executing instructions corresponding to a plurality of instruction lines of an operation algorithm for the data operation and, when a suspend command is provided during the data operation, to perform a preset suspend operation in any one of a checker mode and an instant mode.

Abstract: The semiconductor memory device includes: a memory unit including a plurality of memory blocks; a decoder suitable for storing bad block information about the plurality of memory blocks, and outputting the bad block information in response to an address signal; and a control logic suitable for controlling the memory unit and the decoder to update a status register (SR) code in response to the bad block information when the semiconductor memory device at a ready state enters a busy state, and to perform a general operation according to the updated SR code and a command.

Abstract: A semiconductor device and a method of operating the same are provided. The method includes performing a multi-plane erase operation on selected planes; determining that the multi-plane erase operation has failed when a number of erase loops reaches a maximum number without successful completion of the multi-plane erase operation; determining whether there are passed planes amongst the selected planes; and performing a soft program operation on the passed planes.

Abstract: A method of operating a semiconductor device includes dividing an operation of the semiconductor device into a plurality of periods, and determining a plurality of state codes respectively corresponding to the periods; performing the operation according to a received command; when a pause command is received, pausing the operation and storing a state code of the plurality of state codes corresponding to a paused period among the plurality of periods; and performing the operation starting from a period determined according to the stored state code when a resumption command is received.

Abstract: A semiconductor device and a method of operating the same are provided. The method includes performing a multi-plane erase operation on selected planes; determining that the multi-plane erase operation has failed when a number of erase loops reaches a maximum number without successful completion of the multi-plane erase operation; determining whether there are passed planes amongst the selected planes; and performing a soft program operation on the passed planes.

Abstract: A method of operating a semiconductor device includes dividing an operation of the semiconductor device into a plurality of periods, and determining a plurality of state codes respectively corresponding to the periods; performing the operation according to a received command; when a pause command is received, pausing the operation and storing a state code of the plurality of state codes corresponding to a paused period among the plurality of periods; and performing the operation starting from a period determined according to the stored state code when a resumption command is received.

Abstract: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.

Abstract: A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage distribution, to compare the measured threshold voltage distribution with a reference threshold voltage distribution, and to determine a read voltage having a least amount of errors upon the read operation being performed.

Abstract: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.

Abstract: A nonvolatile memory device includes a storage unit configured to store pattern data selected based on a test command set, and a control unit configured to consecutively perform a program operation on a number of pages in response to the pattern data to obtain programmed pages, consecutively perform a read operation on the programmed pages, and provide information about a bit line coupled to a fail memory cell and about a number of fail bit lines checked as a result of the read operation.

Abstract: An operation method of a nonvolatile memory device includes reading information of an erase target block, and performing an erase operation by using a starting erase bias corresponding to the information.

Abstract: A nonvolatile memory device includes a storage unit configured to store pattern data selected based on a test command set, and a control unit configured to consecutively perform a program operation on a number of pages in response to the pattern data to obtain programmed pages, consecutively perform a read operation on the programmed pages, and provide information about a bit line coupled to a fail memory cell and about a number of fail bit lines checked as a result of the read operation.