Abstract: A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.

Abstract: A memory device including a substrate, a plurality of conductive layers, a composite dielectric layer and a plurality of gates are provided. Wherein, the conductive layers are disposed on the substrate. The composite dielectric layer is disposed on the substrate and covers the conductive layers. The composite dielectric layer includes a charge trapping layer. The gates are disposed on the composite dielectric layer and across the conductive layers. Wherein, the conductive layers can be used as local bit lines to reduce the resistance values and improve the performance of the memory device.

Abstract: A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.

Abstract: A memory device including a substrate, a plurality of conductive layers, a composite dielectric layer and a plurality of gates are provided. Wherein, the conductive layers are disposed on the substrate. The composite dielectric layer is disposed on the substrate and covers the conductive layers. The composite dielectric layer includes a charge trapping layer. The gates are disposed on the composite dielectric layer and across the conductive layers. Wherein, the conductive layers can be used as local bit lines to reduce the resistance values and improve the performance of the memory device.

Abstract: A method for dynamically adjusting the operation of a memory chip is disclosed. First, a memory chip is provided. The memory chip comprises an ONO layer. Then, the thickness of the ONO layer in the memory chip is measured, and a read word line voltage of the memory chip is then adjusted based on the measured thickness of the ONO layer. Since the operation window of memory chip is dynamically adjusted, a more reliable product operation and a sufficient mass production window are obtained.

Abstract: A method for dynamically adjusting the operation of a memory chip is disclosed. First, a memory chip is provided. The memory chip comprises an ONO layer. Then, the thickness of the ONO layer in the memory chip is measured, and a read word line voltage of the memory chip is then adjusted based on the measured thickness of the ONO layer. Since the operation window of memory chip is dynamically adjusted, a more reliable product operation and a sufficient mass production window are obtained.

Abstract: A method for fabricating a nitride read-only memory is described. An ONO stacked layer and a protective layer are sequentially formed on a substrate. A patterning/etching process is performed to pattern the protective layer and the ONO stacked layer to expose a portion of the substrate. Thereafter, the protective layer is removed by using wet etching. An ion implantation is performed to form buried bit lines in the exposed substrate, and then an insulator is formed on each buried bit line. A plurality of word lines are formed on the substrate crossing over the buried bit lines.

Abstract: A method for fabricating a nitride read-only memory is described. An ONO stacked layer and a protective layer are sequentially formed on a substrate. A patterning/etching process is performed to pattern the protective layer and the ONO stacked layer to expose a portion of the substrate. Thereafter, the protective layer is removed by using wet etching. An ion implantation is performed to form buried bit lines in the exposed substrate, and then an insulator is formed on each buried bit line. A plurality of word lines are formed on the substrate crossing over the buried bit lines.

Abstract: The present invention provides a method for operating a NROM device, where the source and drain are surrounded by a heavy doping. When programming the NROM device, a more positive source bias and a more negative substrate bias is used to increase the body effect of the substrate for reducing the current require for Channel Hot Electron Injection (CHEI) programming. Furthermore, before erasing the NROM array, a pre-programming operation is performed to program every single memory cell of the NROM array to the written state for preventing over-erasing of the memory cells.

Abstract: A fabrication method for a mask read-only memory includes forming an oxide layer on a provided substrate. A first mask layer is formed on the oxide layer, followed by performing a first ion implantation to form a plurality of equally spaced bit lines. A thermal process is further conducted to convert the oxide layer to a denser oxide layer. A plurality of word lines, which is perpendicular to the bit lines, is formed on the denser oxide layer. A second mask layer is formed on the plurality of the word lines, exposing the channel to be coded. A second ion implantation is conducted on the channel to complete the fabrication of the mask read-only memory device.

Abstract: A fabrication method for a mask read-only memory includes forming an oxide layer on a provided substrate. A first mask layer is formed on the oxide layer, followed by performing a first ion implantation to form a plurality of equally spaced bit lines. A thermal process is further conducted to convert the oxide layer to a denser oxide layer. A plurality of word lines, which is perpendicular to the bit lines, is formed on the denser oxide layer. A second mask layer is formed on the plurality of the word lines, exposing the channel to be coded. A second ion implantation is conducted on the channel to complete the fabrication of the mask read-only memory device.