Patents by Inventor Tai Ly

Tai Ly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070230645
    Abstract: During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.
    Type: Application
    Filed: June 7, 2007
    Publication date: October 4, 2007
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventors: Tai Ly, Ka Kwok, Vijaya Gupta, Ross Andersen, Ping Yeung, Neil Hand, Lawrence Widdoes
  • Publication number: 20050268265
    Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
    Type: Application
    Filed: May 27, 2005
    Publication date: December 1, 2005
    Applicant: Mentor Graphics Corporation
    Inventors: Tai Ly, Ka Kwok, Vijaya Gupta, Lawrence Widdoes
  • Publication number: 20050131665
    Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.
    Type: Application
    Filed: January 12, 2005
    Publication date: June 16, 2005
    Inventors: Chian-Min Ho, Robert Mardjuki, David Dill, Jing Lin, Ping Yeung, Paul Estrada, Jean-Charles Giomi, Tai Ly, Kalyana Mulam, Lawrence Widdoes, Paul Wilcox