Patents by Inventor Tai Min

Tai Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250060676
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Patent number: 12221701
    Abstract: A welded member includes: a first steel sheet including a base steel sheet and a zinc-based plating layer formed on a surface of the base steel sheet; and a second steel sheet spot-welded on the first steel sheet and facing the zinc-based plating layer of the first steel sheet, a spot-welded zone being formed between the first steel sheet and the second steel sheet. A surface layer of the base steel sheet has a decarburization ratio of 30% or more. The decarburization ratio is represented by equation: Decarburization ratio (%) of surface layer=(1?average carbon concentration in surface layer/bulk carbon concentration)*100 where the surface layer refers to a region of the base steel sheet from the surface thereof to a depth of 35 ?m. A shoulder portion of the spot-welded zone includes a B-type crack having a length of 100 ?m or less, and no C-type crack.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: February 11, 2025
    Assignee: POSCO CO., LTD
    Inventors: Ki-Cheol Kang, Sang-Ho Uhm, Chang-Woon Jee, Yeon-Chae Jeong, Kwang-Tai Min
  • Publication number: 20250034692
    Abstract: An aluminum alloy-plated steel sheet having excellent workability and corrosion resistance and a method for manufacturing the same are disclosed. The aluminum alloy-plated steel sheet includes a base sheet, and an alloy-plated layer formed on the base sheet. Interfacial roughness between the alloy-plated layer and the base steel sheet is 25 ?m or less. Such an aluminum alloy-plated steel sheet prevents microcracks generated during hot forming and has excellent seizure resistance and corrosion resistance. A method for manufacturing such an aluminum alloy-plated steel is also disclosed.
    Type: Application
    Filed: October 17, 2024
    Publication date: January 30, 2025
    Applicant: POSCO Co., Ltd.
    Inventors: Suk-Kyu Lee, Hyeon-Seok Hwang, Myung-Soo Kim, Jong-Gi Oh, Kwang-Tai Min
  • Publication number: 20250029946
    Abstract: A package structure includes an integrated circuit die and an encapsulant laterally encapsulating the integrated circuit die. The integrated circuit die includes a semiconductor substrate, an interconnection structure, a testing pad, a dummy post, a conductive post, and a protection layer. The interconnection structure is disposed on the semiconductor substrate. The testing pad is disposed on the interconnection structure. The dummy post is disposed on the testing pad. The conductive post is aside the dummy post. The protection layer is disposed between the conductive post and the dummy post.
    Type: Application
    Filed: October 3, 2024
    Publication date: January 23, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Patent number: 12164232
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Publication number: 20240404876
    Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.
    Type: Application
    Filed: July 30, 2024
    Publication date: December 5, 2024
    Inventors: Kan-Ju Lin, Chien Chang, Chih-Shiun Chou, Tai Min Chang, Yi-Ning Tai, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Lin-Yu Huang
  • Patent number: 12152305
    Abstract: An aluminum alloy-plated steel sheet having excellent workability and corrosion resistance and a method for manufacturing the same are disclosed. The aluminum alloy-plated steel sheet that includes a base sheet, and an alloy-plated layer formed on the base sheet. Interfacial roughness between the alloy-plated layer and the base steel sheet is 25. ?m or less. Such an aluminum alloy-plated steel sheet prevents microcracks generated during hot forming and has excellent seizure resistance and corrosion resistance. A method for manufacturing such an aluminum alloy-plated steel is also disclosed.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 26, 2024
    Assignee: POSCO
    Inventors: Suk-Kyu Lee, Hyeon-Seok Hwang, Myung-Soo Kim, Jong-Gi Oh, Kwang-Tai Min
  • Publication number: 20240379423
    Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 12132023
    Abstract: An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, dummy posts, and a protection layer. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads and are electrically floating. The protection layer covers the conductive posts and the dummy posts. A distance between top surfaces of the conductive posts and a top surface of the protection layer is smaller than a distance between top surfaces of the dummy posts and the top surface of the protection layer.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20240282653
    Abstract: Provided is a package structure including a first die and an encapsulant. The first die includes a substrate, a plurality of pads over the substrate, a passivation layer on portions of each of the plurality of pads, a plurality of first die connectors on the plurality of pads, respectively and a dielectric layer laterally encapsulating the plurality of first die connectors. The encapsulant laterally encapsulates the first die. One of the plurality of first die connectors is a taper-shaped die connector. A width of the one of the plurality of first die connectors gradually increases from a top surface of the one of the plurality of first die connectors toward the a top surface of the passivation layer.
    Type: Application
    Filed: May 1, 2024
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20240240299
    Abstract: A welded member includes: a first steel sheet including a base steel sheet and a zinc-based plating layer formed on a surface of the base steel sheet; and a second steel sheet spot-welded on the first steel sheet and facing the zinc-based plating layer of the first steel sheet, a spot-welded zone being formed between the first steel sheet and the second steel sheet. A surface layer of the base steel sheet has a decarburization ratio of 30% or more. The decarburization ratio is represented by equation: Decarburization ratio (%) of surface layer=(1?average carbon concentration in surface layer/bulk carbon concentration)*100 where the surface layer refers to a region of the base steel sheet from the surface thereof to a depth of 35 ?m. A shoulder portion of the spot-welded zone includes a B-type crack having a length of 100 ?m or less, and no C-type crack.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Ki-Cheol KANG, Sang-Ho UHM, Chang-Woon JEE, Yeon-Chae JEONG, Kwang-Tai MIN
  • Patent number: 11990383
    Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20240052495
    Abstract: The present disclosure relates to an aluminum alloy-plated steel sheet having excellent workability and corrosion resistance and a method for manufacturing the same, and more particularly, to an aluminum alloy-plated steel sheet that prevents microcracks generated during hot forming and has excellent seizure resistance and corrosion resistance, and a method for manufacturing the same.
    Type: Application
    Filed: December 18, 2020
    Publication date: February 15, 2024
    Applicant: POSCO
    Inventors: Suk-Kyu Lee, Hyeon-Seok Hwang, Myung-Soo Kim, Jong-Gi Oh, Kwang-Tai Min
  • Patent number: 11898252
    Abstract: The present disclosure relates to an aluminum alloy-plated steel sheet having excellent workability and corrosion resistance and a method for manufacturing the same, and more particularly, to an aluminum alloy-plated steel sheet preventing microcracks generated during hot forming and has excellent seizure resistance and corrosion resistance, and a method for manufacturing the same.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 13, 2024
    Assignee: POSCO
    Inventors: Suk-Kyu Lee, Hyeon-Seok Hwang, Myung-Soo Kim, Kwang-Tai Min, Dae-Young Kang
  • Publication number: 20240011119
    Abstract: An embodiment of the present invention provides a high strength hot-dip galvanized steel sheet having excellent plating adhesion and weldability and a method of manufacturing same, wherein: the steel sheet comprises a base steel sheet and a hot-dip galvanized layer formed on one surface or both surfaces of the base steel sheet, the base steel sheet comprising, in weight %, carbon (C): 0.1-0.3%, silicon (Si): 0.1-2.0%, aluminum (Al): 0.1-1.5%, manganese (Mn): 1.5-3.0%, and the balance being Fe and inevitable impurities, the sum of Si and Al satisfying 1.2-3.5%, the ratio (Al/Si) of Al and Si satisfying 0.5-2.0; the steel sheet comprises an internal oxidation layer with a thickness of 1-5 ?m directly below the surface of the base steel sheet; and the decarburization rate in a region from directly below the surface of the base steel sheet to 50 ?m is 50% or more.
    Type: Application
    Filed: December 9, 2021
    Publication date: January 11, 2024
    Applicant: POSCO Co., Ltd
    Inventors: Young-Ha Kim, Myung-Soo Kim, Kwang-Tai Min, Ki-Cheol Kang
  • Patent number: 11870105
    Abstract: A planar type solid oxide fuel cell, and more particularly, a thin and light planar type solid oxide fuel cell omits a window frame and has a simplified a unit cell having a through hole through which fuel and air flow in/out a fuel electrode.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: January 9, 2024
    Assignee: LG CHEM, LTD.
    Inventors: Tai Min Noh, Sanghyeok Im, Yeonhyuk Heo, Kwangyeon Park, Kwangwook Choi
  • Patent number: 11855309
    Abstract: An interconnect for a solid oxide fuel cell, its manufacturing method, and a solid oxide fuel cell including the same are provided.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 26, 2023
    Assignee: LG CHEM, LTD.
    Inventors: Tai Min Noh, Daehwan Kim, Chanyeup Chung, Sanghyun Park, Changseok Ryoo, Kwangwook Choi
  • Publication number: 20230411496
    Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 21, 2023
    Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Yi-Ning TAI, Hong-Mao LEE, Yan-Ming TSAI, Wei-Yip LOH, Harry CHIEN, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
  • Patent number: 11848233
    Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
    Type: Grant
    Filed: March 27, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
  • Publication number: 20230384684
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang