Abstract: A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single field effect transistor (FET) switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives.

Abstract: A multiplying circuit comprises an array circuit for producing a product of a multiplicand and multiplier by adding respective partial products together each of a multiplicand in each bit and a multiplier in each bit. The array circuit produces only an (n+1) or more bits of the product, where n denotes a positive integer which is not greater than the bit number of the multiplicand and the bit number of the multiplier. The multiplying circuit comprises a circuit for producing a binary compensation signal representing an integral value closest to a real number given by{(n-1)+(1/2.sup.n)}/2and a circuit for adding the compensation signal to the output from the array circuit.