Patents by Inventor TAI-YU CHENG
TAI-YU CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367358Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Patent number: 11437319Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: GrantFiled: October 8, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Patent number: 11176305Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, the information including a mean of slacks and a sigma of slacks of each of the paths; determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma; dividing the paths into groups based on SM values, an SM value of a path in one of the groups being different from that of a path in another one of the groups; and determining a yield requirement that indicates the maximum number of paths allowable in each group in order to achieve a predetermined yield.Type: GrantFiled: May 19, 2020Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang
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Publication number: 20210028108Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: ApplicationFiled: October 8, 2020Publication date: January 28, 2021Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Patent number: 10804200Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: GrantFiled: November 26, 2018Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Publication number: 20200279068Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, the information including a mean of slacks and a sigma of slacks of each of the paths; determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma; dividing the paths into groups based on SM values, an SM value of a path in one of the groups being different from that of a path in another one of the groups; and determining a yield requirement that indicates the maximum number of paths allowable in each group in order to achieve a predetermined yield.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: YEN-PIN CHEN, TZU-HEN LIN, TAI-YU CHENG, FLORENTIN DARTU, CHUNG-HSING WANG
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Patent number: 10678989Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.Type: GrantFiled: January 18, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang
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Patent number: 10515166Abstract: A method includes identifying the first path as a target path, wherein an operation speed of the target path is adjusted from the corner case; deriving and outputting first values from the lookup table by indexing the lookup table with a threshold voltage associated with the first path identified as the target path as the main threshold voltage and a threshold voltage associated with the second path as the slave threshold voltage; calculating a first extra time based on the first values and first cell delays associated with the first path.Type: GrantFiled: January 18, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Pin Chen, Tai-Yu Cheng, Tzu-Hen Lin, Chung-Hsing Wang
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Publication number: 20190096805Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Patent number: 10176284Abstract: A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component; obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.Type: GrantFiled: September 30, 2016Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Li-Chung Hsu, Tai-Yu Cheng, Sung-Yen Yeh, King-Ho Tam, Yen-Pin Chen, Chung-Hsing Wang
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Patent number: 10157840Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: GrantFiled: March 24, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Publication number: 20180247007Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.Type: ApplicationFiled: January 18, 2018Publication date: August 30, 2018Inventors: YEN-PIN CHEN, TZU-HEN LIN, TAI-YU CHENG, FLORENTIN DARTU, CHUNG-HSING WANG
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Publication number: 20180232474Abstract: A method includes identifying the first path as a target path, wherein an operation speed of the target path is adjusted from the corner case; deriving and outputting first values from the lookup table by indexing the lookup table with a threshold voltage associated with the first path identified as the target path as the main threshold voltage and a threshold voltage associated with the second path as the slave threshold voltage; calculating a first extra time based on the first values and first cell delays associated with the first path.Type: ApplicationFiled: January 18, 2018Publication date: August 16, 2018Inventors: YEN-PIN CHEN, TAI-YU CHENG, TZU-HEN LIN, CHUNG-HSING WANG
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Publication number: 20180158776Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: ApplicationFiled: March 24, 2017Publication date: June 7, 2018Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Publication number: 20180096087Abstract: A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component, obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: LI-CHUNG HSU, TAI-YU CHENG, SUNG-YEN YEH, KING-HO TAM, YEN-PIN CHEN, CHUNG-HSING WANG