Patents by Inventor Tai-Yuan Tseng
Tai-Yuan Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180197586Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.Type: ApplicationFiled: June 16, 2017Publication date: July 12, 2018Applicant: SanDisk Technologies LLCInventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
-
Patent number: 10014063Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.Type: GrantFiled: October 30, 2015Date of Patent: July 3, 2018Assignee: SanDisk Technologies LLCInventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
-
Patent number: 9892791Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.Type: GrantFiled: June 16, 2016Date of Patent: February 13, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Yen-Lung Li, Jong Yuh, Jonathan Huynh, Tai-Yuan Tseng, Kwang-Ho Kim, Qui Nguyen
-
Patent number: 9881676Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.Type: GrantFiled: October 11, 2016Date of Patent: January 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jong Hak Yuh, Raul Adrian Cernea, Seungpil Lee, Yen-Lung Jason Li, Qui Nguyen, Tai-Yuan Tseng, Cynthia Hsu
-
Patent number: 9754645Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.Type: GrantFiled: October 27, 2015Date of Patent: September 5, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Anirudh Amarnath, Tai-Yuan Tseng
-
Patent number: 9711211Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.Type: GrantFiled: October 29, 2015Date of Patent: July 18, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta
-
Publication number: 20170125087Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.Type: ApplicationFiled: October 29, 2015Publication date: May 4, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta
-
Publication number: 20170125117Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
-
Publication number: 20170117024Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: Anirudh Amarnath, Tai-Yuan Tseng
-
Patent number: 9595317Abstract: A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.Type: GrantFiled: October 30, 2015Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventors: Yen-Lung Li, Raul-Adrian Cernea, Jong Hak Yuh, Tai-Yuan Tseng
-
Patent number: 9552882Abstract: A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.Type: GrantFiled: February 6, 2015Date of Patent: January 24, 2017Assignee: SanDisk Technologies LLCInventors: Tai-Yuan Tseng, Yenlung Li, Cynthia Hsu, Kwang Ho Kim, Man L Mui
-
Patent number: 9543030Abstract: Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is ramping up and then transfer the result into a data latch. In contrast, with conventional sensing, a bit line of the memory array may be first precharged to a particular voltage level (e.g., a read voltage level) and then sensed while the word line is held at the particular voltage level.Type: GrantFiled: October 27, 2015Date of Patent: January 10, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Anirudh Amarnath, Tai-Yuan Tseng
-
Publication number: 20160372200Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.Type: ApplicationFiled: June 16, 2016Publication date: December 22, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yen-Lung Li, Jong Yuh, Jonathan Huynh, Tai-Yuan Tseng, Kwang-Ho Kim, Qui Nguyen
-
Publication number: 20160372205Abstract: Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is ramping up and then transfer the result into a data latch. In contrast, with conventional sensing, a bit line of the memory array may be first precharged to a particular voltage level (e.g., a read voltage level) and then sensed while the word line is held at the particular voltage level.Type: ApplicationFiled: October 27, 2015Publication date: December 22, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Anirudh Amarnath, Tai-Yuan Tseng
-
Publication number: 20160351254Abstract: A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.Type: ApplicationFiled: October 30, 2015Publication date: December 1, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yen-Lung Li, Raul-Adrian Cernea, Jong Hak Yuh, Tai-Yuan Tseng
-
Patent number: 9437302Abstract: A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.Type: GrantFiled: February 6, 2015Date of Patent: September 6, 2016Assignee: SanDisk Technologies LLCInventors: Tai-Yuan Tseng, Cynthia Hsu, Kwang Ho Kim
-
Publication number: 20150221391Abstract: A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.Type: ApplicationFiled: February 6, 2015Publication date: August 6, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Tai-Yuan Tseng, Cynthia Hsu, Kwang Ho Kim
-
Publication number: 20150221348Abstract: A non-volatile memory includes an efficient data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.Type: ApplicationFiled: February 6, 2015Publication date: August 6, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Tai-Yuan Tseng, Yenlung Li, Cynthia Hsu, Kwang Ho Kim, Man L. Mui
-
Patent number: 7663950Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.Type: GrantFiled: June 27, 2008Date of Patent: February 16, 2010Assignee: Sandisk CorporationInventors: Farookh Moogat, Raul-Adrian Cernea, Shou-Chang Tsao, Tai-Yuan Tseng
-
Patent number: 7518837Abstract: A control device for soft starting and protecting overload of a motor in a power tool is disclosed. The control device comprises a power switch, a varistor, several diodes, several resistors, several capacitors, a relay, a transistor, a triac, and a microcontroller. The microcontroller is embedded with program such that, after the power switch is turned on, the microcontroller generates a smooth soft start voltage to drive the power tool. With the characteristics of power-control device, the voltage sent to motor is increased from low to full range. When the speed of motor is increased from low to the maximum, the microcontroller turns off the power-control device and turns on a relay.Type: GrantFiled: September 21, 2006Date of Patent: April 14, 2009Assignee: Uan Chung Enterprises Co., LtdInventors: Tai-Yuan Tseng, Mu-Hsien Huang