Patents by Inventor Tai-Yuan Wang

Tai-Yuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395682
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternately stacking first sacrificial layers and first channel layers. The method also includes forming source/drain features on opposite sidewalls of the fin structure, etching the fin structure to form gate recesses in the fin structure, removing the first sacrificial layers of the fin structure from the gate recesses, thereby forming first gaps exposing the first channel layers, and forming a gate stack in the gate recesses and the first gaps.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventor: Tai-Yuan WANG
  • Patent number: 11754586
    Abstract: A wind speed detection system and a wind speed detection method are provided. The wind speed detection system includes a pipe body and a controller. The pipe body comprises a pressure sensing module and a suction pump. The pressure sensing module is connected to a first opening through a first pipe and connected to a second opening through a second pipe. The first pipe has a main pipe. Two ends of a first alternative pipe are connected to two ends of the main pipe. When the controller performs a self-checking operation, the main pipe is closed and the first alternative pipe is opened. The controller starts the suction pump to perform forward suction. The controller measures a first air pressure through the first pipe and measures a second air pressure through the second pipe by the pressure sensing module. The controller calculates a reference wind speed value according to the first and second air pressures.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: September 12, 2023
    Assignee: Coretronic Intelligent Robotics Corporation
    Inventors: Ying-Chieh Chen, Tai-Yuan Wang, I-Ta Yang
  • Publication number: 20220365108
    Abstract: A wind speed detection system and a wind speed detection method are provided. The wind speed detection system includes a pipe body, a pressure sensing module, a suction pump, and a controller. The pressure sensing module is connected to a first opening through a first pipe and connected to a second opening through a second pipe. The first pipe has a main pipe. Two ends of a first alternative pipe are connected to two ends of the main pipe. When the controller performs a self-checking operation, the main pipe is closed and the first alternative pipe is opened. The controller starts the suction pump to perform forward suction. The controller measures a first air pressure through the first pipe and measures a second air pressure through the second pipe by the pressure sensing module. The controller calculates a reference wind speed value according to the first and second air pressures.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 17, 2022
    Applicant: Coretronic Intelligent Robotics Corporation
    Inventors: Ying-Chieh Chen, Tai-Yuan Wang, I-Ta Yang
  • Patent number: 11478394
    Abstract: An exoskeleton wear management method is provided. The method includes receiving inertial data from a sensing system; determining whether a left leg component of an exoskeleton device is parallel to a left leg of a user and a right leg component of the exoskeleton device is parallel to a right leg of the user according to the received inertial data; in response to determining that the left leg component/the right leg component is not parallel to the left leg/the right leg of the user, prompting an adjusting left leg component message/an adjusting right leg component message; and in response to determining that the left leg component is parallel to the left leg of the user and the right leg component is parallel to the right leg of the user, prompting a left leg component and right leg component correctly-worn message.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 25, 2022
    Assignee: Wistron Corporation
    Inventors: Tsung-Yin Tsou, Min-Yen Li, Tai-Yuan Wang, Hong-Siou Chen
  • Publication number: 20220320279
    Abstract: A method of forming a semiconductor device includes forming a first semiconductor strip protruding above a first region of a substrate and a second semiconductor strip protruding above a second region of the substrate, forming an isolation region between the first semiconductor strip and the second semiconductor strip, forming a gate stack over and along sidewalls of the first semiconductor strip and the second semiconductor strip, etching a trench extending into the gate stack and isolation regions, the trench exposing the first region of the substrate and the second region of the substrate, forming a dielectric layer on sidewalls and a bottom surface of the trench and filling a conductive material over the dielectric layer and in the trench to form a contact, where the contact extends below a bottommost surface of the isolation region.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 6, 2022
    Inventors: Tai-Yuan Wang, Shu-Fang Chen
  • Patent number: 11404577
    Abstract: A method includes forming a dielectric cap over a semiconductor substrate; forming a dummy gate structure over the dielectric cap; forming gate spacers on opposite sidewalls of the dummy gate structure and on a top surface of the dielectric cap; removing the dummy gate structure to form a gate trench between the gate spacers and exposing the dielectric cap; and performing an ion implantation to form a doped region in the semiconductor substrate through the dielectric cap.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 11374089
    Abstract: A method of forming a semiconductor device includes forming a first semiconductor strip protruding above a first region of a substrate and a second semiconductor strip protruding above a second region of the substrate, forming an isolation region between the first semiconductor strip and the second semiconductor strip, forming a gate stack over and along sidewalls of the first semiconductor strip and the second semiconductor strip, etching a trench extending into the gate stack and isolation regions, the trench exposing the first region of the substrate and the second region of the substrate, forming a dielectric layer on sidewalls and a bottom surface of the trench and filling a conductive material over the dielectric layer and in the trench to form a contact, where the contact extends below a bottommost surface of the isolation region.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yuan Wang, Shu-Fang Chen
  • Publication number: 20220001994
    Abstract: A drone includes a drone main body and a parachute module. The parachute module includes a base, a housing, an inflatable material, a parachute, and an inflating device. The base is disposed on the drone main body. The housing covers the base to form a containing space therebetween. The inflatable material is disposed on the base and furled in the containing space. The parachute is connected to the inflatable material and the housing and is furled in the containing space. The inflating device is disposed on the base and connected to the inflatable material. When the inflating device inflates the inflatable material, the inflatable material expands and strikes the housing, so that the housing is separated from the drone main body, so as to increase a distance between the parachute and the drone main body and deploy the parachute. In addition, a control method of the drone is also provided.
    Type: Application
    Filed: June 9, 2021
    Publication date: January 6, 2022
    Applicant: Coretronic Intelligent Robotics Corporation
    Inventors: Ying-Chieh Chen, Tai-Yuan Wang, I-Ta Yang, Chun-Hsu Lai
  • Publication number: 20210367033
    Abstract: A method of forming a semiconductor device includes forming a first semiconductor strip protruding above a first region of a substrate and a second semiconductor strip protruding above a second region of the substrate, forming an isolation region between the first semiconductor strip and the second semiconductor strip, forming a gate stack over and along sidewalls of the first semiconductor strip and the second semiconductor strip, etching a trench extending into the gate stack and isolation regions, the trench exposing the first region of the substrate and the second region of the substrate, forming a dielectric layer on sidewalls and a bottom surface of the trench and filling a conductive material over the dielectric layer and in the trench to form a contact, where the contact extends below a bottommost surface of the isolation region.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventors: Tai-Yuan Wang, Shu-Fang Chen
  • Publication number: 20210022943
    Abstract: An exoskeleton wear management method is provided. The method includes receiving inertial data from a sensing system; determining whether a left leg component of an exoskeleton device is parallel to a left leg of a user and a right leg component of the exoskeleton device is parallel to a right leg of the user according to the received inertial data; in response to determining that the left leg component/the right leg component is not parallel to the left leg/the right leg of the user, prompting an adjusting left leg component message/an adjusting right leg component message; and in response to determining that the left leg component is parallel to the left leg of the user and the right leg component is parallel to the right leg of the user, prompting a left leg component and right leg component correctly-worn message.
    Type: Application
    Filed: October 14, 2019
    Publication date: January 28, 2021
    Applicant: Wistron Corporation
    Inventors: Tsung-Yin Tsou, Min-Yen Li, Tai-Yuan Wang, Hong-Siou Chen
  • Publication number: 20200350436
    Abstract: A method includes forming a dielectric cap over a semiconductor substrate; forming a dummy gate structure over the dielectric cap; forming gate spacers on opposite sidewalls of the dummy gate structure and on a top surface of the dielectric cap; removing the dummy gate structure to form a gate trench between the gate spacers and exposing the dielectric cap; and performing an ion implantation to form a doped region in the semiconductor substrate through the dielectric cap.
    Type: Application
    Filed: July 13, 2020
    Publication date: November 5, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan WANG
  • Patent number: 10714621
    Abstract: A semiconductor device includes a plurality of gate spacers, a gate conductor, and first and semiconductor features. The gate conductor is between the gate spacers. The first semiconductor feature underlies the gate conductor and has impurities therein. The second semiconductor feature underlies at least one of the gate spacers and substantially free from the impurities of the first semiconductor feature.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 10672867
    Abstract: A method includes forming a fin structure over a substrate; forming an isolation structure around the fin structure; etching the fin structure to form a recess in the fin structure; epitaxially growing a source drain structure in the recess; depositing a capping layer over a first portion of the source drain structure, in which the first portion of the source drain structure is over the isolation structure; recessing the isolation structure to expose a second portion of the source drain structure; and etching the second portion of the source drain structure, in which the first portion of the source drain structure remains over the isolation structure after etching the second portion of the source drain structure.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Publication number: 20190096995
    Abstract: A method includes forming a fin structure over a substrate; forming an isolation structure around the fin structure; etching the fin structure to form a recess in the fin structure; epitaxially growing a source drain structure in the recess; depositing a capping layer over a first portion of the source drain structure, in which the first portion of the source drain structure is over the isolation structure; recessing the isolation structure to expose a second portion of the source drain structure; and etching the second portion of the source drain structure, in which the first portion of the source drain structure remains over the isolation structure after etching the second portion of the source drain structure.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 28, 2019
    Inventor: Tai-Yuan WANG
  • Publication number: 20180350907
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one source drain structure, an insulating layer, and a gate. The semiconductor substrate includes a base portion and at least one fin. The fin is disposed on the base portion. The source drain structure is disposed on at least one sidewall of the fin. The insulating layer is disposed between the base portion and the source drain structure to isolate the base portion and the source drain structure. The gate is disposed on the fin.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventor: Tai-Yuan WANG
  • Patent number: 10147787
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one source drain structure, an insulating layer, and a gate. The semiconductor substrate includes a base portion and at least one fin. The fin is disposed on the base portion. The source drain structure is disposed on at least one sidewall of the fin. The insulating layer is disposed between the base portion and the source drain structure to isolate the base portion and the source drain structure. The gate is disposed on the fin.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Publication number: 20180166576
    Abstract: A semiconductor device includes a plurality of gate spacers, a gate conductor, and first and semiconductor features. The gate conductor is between the gate spacers. The first semiconductor feature underlies the gate conductor and has impurities therein. The second semiconductor feature underlies at least one of the gate spacers and substantially free from the impurities of the first semiconductor feature.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventor: Tai-Yuan Wang
  • Patent number: 9923056
    Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Hsiung Lin, Chia-Der Chang, Jung-Ting Chen, Tai-Yuan Wang
  • Publication number: 20170084695
    Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventors: Chih-Hsiung Lin, Chia-Der Chang, Jung-Ting Chen, Tai-Yuan Wang
  • Patent number: 9564510
    Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Hsiung Lin, Chia-Der Chang, Jung-Ting Chen, Tai-Yuan Wang