Abstract: A calibrating method of a phase-locked loop circuit is provided. Firstly, a bias voltage of the phase-locked loop circuit is adjusted, so that the voltage controlled oscillator generates the oscillation signal with an initial frequency. Then, a charging current is used as a driving current and sent to a loop filter. Consequently, a tuned voltage is increased, and the frequency detector issues a first real count number. Then, a discharging current is used as the driving current and sent to the loop filter. Consequently, the tuned voltage is decreased, and the frequency detector issues a second real count number. Then, a ratio of a real loop gain to an ideal loop gain is calculated according to the first real count number and the second real count number. Moreover, a digital filter is adjusted according to the ratio.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistance-capacitance (RC) detection result by performing RC detection on the portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein, wherein the RC detection result corresponds to a detected value representing a product of a resistance value and a capacitance value, and the digital compensation filter includes a gain compensation module and an RC compensation module; and tuning the digital compensation filter by respectively inputting the loop gain calibration result and the RC detection result into the gain compensation module and the RC compensation module. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: A signal generating apparatus includes: a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistance-capacitance (RC) detection result by performing RC detection on the portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein, wherein the RC detection result corresponds to a detected value representing a product of a resistance value and a capacitance value, and the digital compensation filter includes a gain compensation module and an RC compensation module; and tuning the digital compensation filter by respectively inputting the loop gain calibration result and the RC detection result into the gain compensation module and the RC compensation module. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator.

Abstract: A phase locked loop (PLL) directly uses a charge pump and loop filter therein for fast and low-costly calibration. The PLL comprises a charge pump, a loop filter, a voltage comparator, a counting device, and a calibration device. The loop filter comprises a voltage storage device coupled to the charge pump for charging by the charge pump, wherein the voltage storage device comprises a variable impedance. The voltage comparator is coupled to a voltage reference and to the voltage storage device for comparing a voltage of the storage device and a voltage of the voltage reference. The counting device is coupled to the voltage comparator to measure the charge time required for the voltage of the voltage storage device to substantially equal to the voltage of the voltage reference. The calibration device adjusts the variable impedance to adjust the time measured by the counting device to a desired time.

Abstract: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a phase-locked loop device for generating a synthesized signal, wherein the phase-locked loop device includes a phase detector, a charge pump device, a filtering device, a controllable oscillator, and a switch device coupled to the controllable oscillator for selectively coupling the controllable oscillator to the filtering device or a tuning reference signal; a calibration controller generates a tuning reference signal and controls the switch device; and a first calibrator tunes the controllable oscillator into a predetermined sub-band according to a reference oscillating signal and a synthesized signal when the switch device couples the controllable oscillator to the tuning reference signal of the calibration controller.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.

Abstract: A tunable capacitance unit coupled between a pair of circuit nodes. The tunable capacitance unit comprises a tuning input supplying a tuning voltage, and first and second tuning capacitance units. Each of the tuning capacitance units comprises a pair of accumulation-mode MOS varactors with source/drains thereof coupled to the tuning input, a pair of blocking capacitors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective one of the circuit nodes, and a pair of biasing resistors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective bias terminal receiving a respective reference voltage. The reference voltages received by the first and second tuning capacitance units are symmetrical to a predetermined voltage.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.

Abstract: A signal generating apparatus for generating a synthesized signal according to an input signal is provided. The signal generating apparatus includes a phase-locked loop device and a control unit. The phase-locked loop device has a phase/frequency detector for generating a detected signal according to a reference oscillating signal and a feedback signal, a control signal generator for generating a control signal according to the detected signal, a voltage controlled oscillator for generating the synthesized signal according to the control signal, and a divider for dividing the synthesized signal according to a dividing factor to generate the feedback signal. The control unit is for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal. The phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode.

Abstract: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal, the signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a control unit for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal, wherein the phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode; a detecting device for detecting the synthesized signal to generate a calibrating signal in the calibration mode; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered signal; and a modulating device for modulating the filtered signal to generate the dividing factor.

Abstract: A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator.