Abstract: A beam generator, a beam generating method, and a chip are provided. The beam generator comprises a first channel, a second channel, and a signal merging module; the first channel comprises a first-channel filter, the first-channel filter is used to filter an input signal to obtain a first filtered signal; the first filtered signal comprises a desired signal; the second channel comprises: a second-channel blocking module, used to block the desired signal in the input signal to obtain a blocked signal; a compensation filter, connected to the second-channel blocking module for compensating for the blocked signal to obtain a second filtered signal; and an adaptive filter connected to the compensation filter for adaptively filtering the second filtered signal to obtain a third filtered signal; the signal merging module is for merging the first filtered signal and the third filtered signal to obtain an output signal.

Abstract: This application relates to a method for training a speech recognition model, the method comprises: providing a speech training data set comprising a plurality of speech data items and speech tags each corresponding to a speech data item; providing a speech recognition model to be trained, the speech recognition model to be trained comprising a convolution neural network, a first fully connected network, a recurrent neural network and a second fully connected network which are cascade coupled together, wherein each of the networks comprises one or more network layers each having a parameter matrix; and wherein the speech recognition model is configured to process speech data items to generate corresponding speech recognition results; and using the speech training data set to train the speech recognition model such that the parameter matrices of at least two adjacent network layers of the trained speech recognition model satisfies a predetermined constraint condition; and the speech recognition model trained u

Abstract: A beam generator, a beam generating method, and a chip are provided. The beam generator comprises a first channel, a second channel, and a signal merging module; the first channel comprises a first-channel filter, the first-channel filter is used to filter an input signal to obtain a first filtered signal; the first filtered signal comprises a desired signal; the second channel comprises: a second-channel blocking module, used to block the desired signal in the input signal to obtain a blocked signal; a compensation filter, connected to the second-channel blocking module for compensating for the blocked signal to obtain a second filtered signal; and an adaptive filter connected to the compensation filter for adaptively filtering the second filtered signal to obtain a third filtered signal; the signal merging module is for merging the first filtered signal and the third filtered signal to obtain an output signal.

Abstract: A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Abstract: The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Abstract: The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Abstract: A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Abstract: A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.

Abstract: A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.