Abstract: A semiconductor device includes a first conductive part, a second conductive part, a third conductive part, a first insulating part, and a semiconductor part of a first conductivity type. The second conductive part is separated from the first conductive part in a first direction. The third conductive part arranged with a portion of the second conductive part in a second direction crossing the first direction. The first insulating part includes a first insulating region located between the third conductive part and the portion of the second conductive part. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first semiconductor region is located between the first conductive part and the second conductive part. The second semiconductor region is located between the first insulating region and the portion of the second conductive part. The second semiconductor region has a Schottky junction with the second conductive part.

Abstract: A semiconductor device includes a major element including a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member being positioned between the first gate electrode and the first semiconductor region, a gate driver supplying the gate voltage to the first gate electrode, and a recording element electrically connected with the gate driver. The recording element records, as continuously changing analog data, a number of times that the gate voltage is supplied to the first gate electrode while being enough to switch the major element on.

Abstract: A semiconductor device includes a first conductive part, a second conductive part, a third conductive part, a first insulating part, and a semiconductor part of a first conductivity type. The second conductive part is separated from the first conductive part in a first direction. The third conductive part arranged with a portion of the second conductive part in a second direction crossing the first direction. The first insulating part includes a first insulating region located between the third conductive part and the portion of the second conductive part. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first semiconductor region is located between the first conductive part and the second conductive part. The second semiconductor region is located between the first insulating region and the portion of the second conductive part. The second semiconductor region has a Schottky junction with the second conductive part.

Abstract: An embodiment includes a transistor section, a gate electrode pad, a gate connection member, a gate circuit section, and a casing. The transistor section includes a drain electrode, a source electrode and a gate electrode. The transistor section and the gate electrode pad are provided on a semiconductor substrate. The gate connection member connects a gate terminal and the gate electrode pad. The gate circuit section connects the gate electrode pad and the gate electrode, and includes a parallel circuit with a capacitor and a resistive element, a first connection member electrically connecting the capacitor to the gate electrode pad and a second connection member electrically connecting the capacitor to the gate electrode. The casing accommodates the transistor section, the gate electrode pad and the gate circuit section.

Abstract: The major element includes a first electrode, a second electrode, a first semiconductor layer located between the first electrode and the second electrode, the first semiconductor layer forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction. The control element includes a third electrode, a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, the second semiconductor layer forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction.

Abstract: A semiconductor device includes a major element including a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member being positioned between the first gate electrode and the first semiconductor region, and a recording element electrically connected with the first electrode. The recording element records, as analog data, a maximum value of a change amount dV/dt of a voltage of the first electrode over time.

Abstract: A parameter optimization device includes a processing device configured to: generate a partial search space of a second dimensionality from a search space of a first dimensionality, the second dimensionality being less than the first dimensionality; select a plurality of search points in the partial search space by correcting an acquisition function with a local penalty function; and observe, in parallel, a plurality of objective functions corresponding respectively to the plurality of search points.

Abstract: An insulating member includes a fixed charge. The insulating member includes a first insulating part. The first insulating part includes a first region, a second region, and a third region. The first region is positioned between a gate electrode and the second region in a first direction. The second region is positioned between the first region and the third region in the first direction. The third region is positioned between the second region and a second surface in the first direction. A density of the fixed charge is greater in the first region than in the second region.

Abstract: A semiconductor device includes first to third conductive portions, a first insulating portion, and a semiconductor portion. The semiconductor portion includes a first semiconductor region provided between the first conductive portion and the second conductive portion, and a second semiconductor region provided between the second conductive portion and the first insulating region. The second conductive portion includes a first conductive region in Schottky junction with the first semiconductor region, and a second conductive region in Schottky junction with the second semiconductor region. When the first conductivity-type is an n-type, a work function of the first conductive region is smaller than a work function of the second conductive region. When the first conductivity-type is a p-type, the work function of the first conductive region is larger than the work function of the second conductive region.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.