Abstract: A distance image generating device includes a light emitter that emits light pulses; a light receiver that includes light receiving elements and receives reflected light; a distance calculator that generates a distance image based on an amount of the reflected light; and a light amount adjuster that determines an emission count in accordance with which the light emitter is to emit the light pulses and an exposure count in accordance with which the light receiver is to receive the reflected light based on the distance image and causes the light emitter to emit the light pulses in accordance with the determined emission count and the light receiver to receive the reflected light in accordance with the determined exposure count. The distance calculator calculates the distance based on an amount of the reflected light received at the exposure count by the light receiver.

Abstract: A distance-measuring imaging device includes: a drive controller that outputs a light emission control signal for instructing emission of pulsed light and an exposure control signal for instructing exposure to reflected light; an image capturer that includes a plurality of pixels and outputs an exposure signal of each of the plurality of pixels that has been exposed at a timing of the exposure control signal; a pixel calculator that generates a composite signal with a pixel filter that combines exposure signals of adjacent pixels among the plurality of pixels using a weight coefficient for the exposure signal; and a time-of-flight (TOF) calculator that generates a distance image, based on the composite signal. The pixel calculator includes at least two pixel filters having different composite scale factors, and selects the pixel filter from the at least two pixel filters.

Abstract: A distance image generating device includes a light emitter that emits light pulses; a light receiver that includes light receiving elements and receives reflected light; a distance calculator that generates a distance image based on an amount of the reflected light; and a light amount adjuster that determines an emission count in accordance with which the light emitter is to emit the light pulses and an exposure count in accordance with which the light receiver is to receive the reflected light based on the distance image and causes the light emitter to emit the light pulses in accordance with the determined emission count and the light receiver to receive the reflected light in accordance with the determined exposure count. The distance calculator calculates the distance based on an amount of the reflected light received at the exposure count by the light receiver.

Abstract: A communication processor sets a storage request signal to be effective when it is judged that a packet cannot be transmitted and sets the storage request signal to be ineffective when it is judged that the packet can be transmitted. A data processor makes a buffer memory store encoded data therein when it is confirmed that the storage request signal is effective. The data processor reads the encoded data from the buffer memory and transmits the read encoded data to a packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is stored in the buffer memory. The data processor receives the encoded data from the encoder and transmits the received encoded data to the packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is not stored in the buffer memory.

Abstract: An image data transfer method including the steps of: (a) reading pixel data of a two-dimensional image stored in a first image storage and having a plurality of pixels, the position of each of the pixels being represented by coordinates of first and second directions, the pixel data being read by scanning data transfer units of the pixel data in the second direction where each of the data transfer units is formed by data of a predetermined number of pixels consecutive in the first direction; (b) writing the data transfer units read at step (a) in a temporary data storage where data is stored at a position designated by a combination of first and second addresses, the data transfer units being written in burst mode in a region of the temporary data storage in which the first addresses are consecutive while the second address is fixed; and (c) reading the data transfer units written in the temporary data storage from the region in which the first addresses are consecutive while the second address is fixed in b

Abstract: A first data buffer stores LEVEL representing the size of a non-zero coefficient value of the variable length coded/run length coded data input from the outside. A write controller writes the LEVEL to the first data buffer in decoded order. An initial address calculator calculates the initial address of the LEVEL from the TotalCoeff and the number of zero coefficients of the total_zeros. An address holder determines and holds the address of the LEVEL corresponding to data based on the initial address and the number of zero coefficients by the run_before. A read controller reads the LEVEL from the first data buffer based on the address information. A selector selects the data of either the LEVEL stored in the first data buffer or the zero coefficients based on the address information. A post-stage processor post-stage processes the data selected by the selector.

Abstract: An image data processor converts an image signal into an image data. The multi-codec unit converts the image data into a transfer data. A communication unit receives a transfer request from an outside terminal device and transmits the transfer data to the outside terminal device. A time-sharing control unit controls to drive the image data processor and the multi-codec unit in a time-sharing manner in accordance with the transfer request. A transfer data selecting unit for selecting the transfer data corresponding to the transfer request from a group of the transfer data generated by the image data processing unit and the multi-codec unit which are controlled to drive in the time-sharing manner by the time-sharing management unit, and transmitting the selected transfer data to the communication unit.

Abstract: A communication processor sets a storage request signal to be effective when it is judged that a packet cannot be transmitted and sets the storage request signal to be ineffective when it is judged that the packet can be transmitted. A data processor makes a buffer memory store encoded data therein when it is confirmed that the storage request signal is effective. The data processor reads the encoded data from the buffer memory and transmits the read encoded data to a packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is stored in the buffer memory. The data processor receives the encoded data from the encoder and transmits the received encoded data to the packet generator when it is confirmed that the storage request signal is ineffective and the encoded data is not stored in the buffer memory.

Abstract: Image data having a total number of pixels being H×V is written in SDRAM having an enough number of recording domains capable of storing all the pixel data of the image data and the number of Column addresses set therein at 2n (4?n) in the order of lines after the implementation of a first image rotation processing at a rotation angle of 90°×m (0?m?3) to the image data and read from the SDRAM in the order of the lines after the implementation of a second image rotation processing at a rotation angle of 90°×p (0?p?3). In doing so, the recording domains of the SDRAM are divided into a plurality of recording blocks 21-s having the number of the Column addresses set therein at 2q (2?q?(n?2) and capable of storing groups of the pixels for one line in the image data after the implementation of the first image rotation processing. The groups of the pixels for one line in the image data in an image direction after the implementation of the first image rotation processing are written in the recording blocks 21-s.

Abstract: An image data transfer method including the steps of: (a) reading pixel data of a two-dimensional image stored in a first image storage and having a plurality of pixels, the position of each of the pixels being represented by coordinates of first and second directions, the pixel data being read by scanning data transfer units of the pixel data in the second direction where each of the data transfer units is formed by data of a predetermined number of pixels consecutive in the first direction; (b) writing the data transfer units read at step (a) in a temporary data storage where data is stored at a position designated by a combination of first and second addresses, the data transfer units being written in burst mode in a region of the temporary data storage in which the first addresses are consecutive while the second address is fixed; and (c) reading the data transfer units written in the temporary data storage from the region in which the first addresses are consecutive while the second address is fixed in b

Abstract: A first data buffer stores LEVEL representing the size of a non-zero coefficient value of the variable length coded/run length coded data input from the outside. A write controller writes the LEVEL to the first data buffer in decoded order. An initial address calculator calculates the initial address of the LEVEL from the TotalCoeff and the number of zero coefficients of the total_zeros. An address holder determines and holds the address of the LEVEL corresponding to data based on the initial address and the number of zero coefficients by the run_before. A read controller reads the LEVEL from the first data buffer based on the address information. A selector selects the data of either the LEVEL stored in the first data buffer or the zero coefficients based on the address information. A post-stage processor post-stage processes the data selected by the selector.

Abstract: An image data processor converts an image signal into an image data. The multi-codec unit converts the image data into a transfer data. A communication unit receives a transfer request from an outside terminal device and transmits the transfer data to the outside terminal device. A time-sharing control unit controls to drive the image data processor and the multi-codec unit in a time-sharing manner in accordance with the transfer request.

Abstract: A VLC mode judgment section performs judgment on whether or not a received group (Last, Run, Level) exists in a VLC table and then performs judgment on which one of a first escape mode, a second escape more and a third escape mode is suitable. According to a judgment result of the VLC mode judgment section, an FLC processing section or a coding mode selection section performs variable-length coding using selected one of the received group (Last, Run, Level), a group generated in the first escape mode, and a group generated by the second escape group or fixed-length coding using a third escape mode.

Abstract: A VLC mode judgment section performs judgment on whether or not a received group (Last, Run, Level) exists in a VLC table and then performs judgment on which one of a first escape mode, a second escape more and a third escape mode is suitable. According to a judgment result of the VLC mode judgment section, an FLC processing section or a coding mode selection section performs variable-length coding using selected one of the received group (Last, Run, Level), a group generated in the first escape mode, and a group generated by the second escape group or fixed-length coding using a third escape mode.

Abstract: The present invention aims to provide a variable-length coding apparatus that achieves a short processing cycle without causing an increase in circuit scale. Such a variable-length coding apparatus judges whether a VLC table has a variable-length code (VLC) corresponding to a combination (Last, Run, Level), by using an LMAX and an RMAX for the combination (Last, Run, Level). Based on the result of the judgment, the variable-length coding apparatus generates and outputs a code assigned to the combination (Last, Run, Level).

Abstract: A variable length decoding device for decoding variable length coding data and run length coding data according to the present invention comprises a variable length decoding unit 3 for serially decoding the variable length coding data and the run length coding data inputted from outside in a state in which “RUN” representing number of “0” and “LEVEL” representing a magnitude of a coefficient value are combined, a data buffer 4 for storing the “LEVEL”, address retainers 5 and 6 for retaining an address of the “LEVEL” corresponding to the “RUN” based on the number of “0” indicated by the “RUN”, a write control unit 7 for writing the “LEVEL” in the data buffer 4 based on the information of the address retainers, and a read control unit 8 for reading the “LEVEL” from the data buffer 4 based on the information of the address retainers.

Abstract: The present invention aims to provide a variable-length coding apparatus that achieves a short processing cycle without causing an increase in circuit scale. Such a variable-length coding apparatus judges whether a VLC table has a variable-length code (VLC) corresponding to a combination (Last, Run, Level), by using an LMAX and an RMAX for the combination (Last, Run, Level). Based on the result of the judgment, the variable-length coding apparatus generates and outputs a code assigned to the combination (Last, Run, Level).

Abstract: A variable length decoding device for decoding variable length coding data and run length coding data according to the present invention comprises a variable length decoding unit 3 for serially decoding the variable length coding data and the run length coding data inputted from outside in a state in which “RUN” representing number of “0” and “LEVEL” representing a magnitude of a coefficient value are combined, a data buffer 4 for storing the “LEVEL”, address retainers 5 and 6 for retaining an address of the “LEVEL” corresponding to the “RUN” based on the number of “0” indicated by the “RUN”, a write control unit 7 for writing the “LEVEL” in the data buffer 4 based on the information of the address retainers, and a read control unit 8 for reading the “LEVEL” from the data buffer 4 based on the information of the address retainers.

Abstract: Image data having a total number of pixels being H×V is written in SDRAM having an enough number of recording domains capable of storing all the pixel data of the image data and the number of Column addresses set therein at 2n (4?n) in the order of lines after the implementation of a first image rotation processing at a rotation angle of 90°×m (0?m?3) to the image data and read from the SDRAM in the order of the lines after the implementation of a second image rotation processing at a rotation angle of 90°×p (0?p?3). In doing so, the recording domains of the SDRAM are divided into a plurality of recording blocks 21-s having the number of the Column addresses set therein at 2q (2?q?(n?2) and capable of storing groups of the pixels for one line in the image data after the implementation of the first image rotation processing. The groups of the pixels for one line in the image data in an image direction after the implementation of the first image rotation processing are written in the recording blocks 21-s.

Abstract: A CPU (Central Processing Unit) sets an unrewritable area in a nonvolatile memory in accordance with a program for system initialization stored in a boot ROM (Read Only Memory). An access control circuit controls permission/prohibition of rewriting based on a written flag set in the unrewritable area. This allows a system creator to freely write information which needs protection against tampering and also ensures protection against tampering of the information.