Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.

Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.

Abstract: According to one embodiment, an electrostatic discharge semiconductor device includes one or more wiring layers first disposed over a substrate, including: a wiring electrically connected at a first connecting point of a pad, a second wiring electrically connected at a second connecting point of a ground wiring, and a third wiring electrically connected at a third connecting point of the ground wiring; a first transistor formed in the substrate comprising a first diffusion region electrically connected to the first wiring, a second diffusion region electrically connected to the second wiring, and a gate electrically connected to the ground wiring; and a second transistor formed in the substrate comprising the first diffusion region electrically connected to the first wiring, a third diffusion region electrically connected to the third wiring, and a gate electrically connected to the ground wiring, wherein, a first resistance value of a first current pathway leading from the first connecting point to the secon

Abstract: According to one embodiment, an electrostatic discharge semiconductor device includes one or more wiring layers first disposed over a substrate, including: a wiring electrically connected at a first connecting point of a pad, a second wiring electrically connected at a second connecting point of a ground wiring, and a third wiring electrically connected at a third connecting point of the ground wiring; a first transistor formed in the substrate comprising a first diffusion region electrically connected to the first wiring, a second diffusion region electrically connected to the second wiring, and a gate electrically connected to the ground wiring; and a second transistor formed in the substrate comprising the first diffusion region electrically connected to the first wiring, a third diffusion region electrically connected to the third wiring, and a gate electrically connected to the ground wiring, wherein, a first resistance value of a first current pathway leading from the first connecting point to the secon