Abstract: A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.

Abstract: A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.

Abstract: This invention provides a voltage controlled variable gain amplifier circuit that varies its gain linearly and continuously against a gain control voltage VC. The voltage controlled variable gain amplifier circuit includes a first differential amplifier, a second differential amplifier, a gain control voltage/current conversion circuit and a reference current generation circuit. The first differential amplifier and the second differential amplifier are connected in series. The gain control voltage/current conversion circuit converts the gain control voltage VC into a gain control current IC that varies linearly against the gain control voltage VC. Drain currents Id1 and Id2 of first and second differential input transistors vary linearly against the gain control current IC.

Abstract: This invention provides a voltage controlled variable gain amplifier circuit that varies its gain linearly and continuously against a gain control voltage VC. The voltage controlled variable gain amplifier circuit includes a first differential amplifier, a second differential amplifier, a gain control voltage/current conversion circuit and a reference current generation circuit. The first differential amplifier and the second differential amplifier are connected in series. The gain control voltage/current conversion circuit converts the gain control voltage VC into a gain control current IC that varies linearly against the gain control voltage VC. Drain currents Id1 and Id2 of first and second differential input transistors vary linearly against the gain control current IC.

Abstract: The invention provides a level shift circuit that prevents an offset when the supply voltage changes. A level shift circuit has a differential amplification circuit, a current generation circuit, a capacitor and a holding circuit. An input signal from the optical pickup is inputted to the non-inversion input terminal of the differential amplification circuit. First, by turning on a first switch, a feedback loop is formed by the differential amplification circuit, the current generation circuit and the capacitor to perform a level shift, and the voltage charged in the capacitor is held by the holding circuit. Then by turning off the first switch and turning on a second switch, the voltage held by the holding circuit is applied to the non-inversion input terminal of the differential amplification circuit to perform a level shift.

Abstract: The invention provides a charge pump circuit which reduces rise time of an output current even when an input signal is of high frequency. PMOS1 and PMOS2 have gates connected to each other, and the gate of the PMOS1 is connected to the drain thereof. A supply potential (Vdd) is applied to the sources of the PMOS1 and the PMOS2, and the PMOS1 and the PMOS2 form a current mirror circuit. First and second switching elements and a first constant-current source are connected to the drain of the PMOS2. A connection point (a node) of the first switching element and the second switching element is connected to an output terminal. The drain of the PMOS1 is connected to the first constant-current source through a third switching element, and connected to a second constant-current source through a fourth switching element.

Abstract: The invention provides a level shift circuit that prevents an offset when the supply voltage changes. A level shift circuit has a differential amplification circuit, a current generation circuit, a capacitor and a holding circuit. An input signal from the optical pickup is inputted to the non-inversion input terminal of the differential amplification circuit. First, by turning on a first switch, a feedback loop is formed by the differential amplification circuit, the current generation circuit and the capacitor to perform a level shift, and the voltage charged in the capacitor is held by the holding circuit. Then by turning off the first switch and turning on a second switch, the voltage held by the holding circuit is applied to the non-inversion input terminal of the differential amplification circuit to perform a level shift.

Abstract: A combined AD/DA converting apparatus includes an input signal selection circuit configured to select one analog signal out of a plurality of analog input signals based on an input selection signal; an input sample hold circuit configured to sample and hold the analog input signal; a DA converter configured to convert a digital signal into an analog signal; a comparator circuit configured to output a comparison signal that indicates a size relation between the analog input signal and the analog signal; a sequential comparison register configured to define sequentially each place of a digital signal stored in the register based on the comparison signal; and a selection circuit configured to output the digital signal to the DA converter when the conversion selection signal indicates AD conversion, and to output the digital input signal to the DA converter when the conversion selection signal indicates DA conversion.

Abstract: The invention provides a charge pump circuit which reduces rise time of an output current even when an input signal is of high frequency. PMOS1 and PMOS2 have gates connected to each other, and the gate of the PMOS1 is connected to the drain thereof. A supply potential (Vdd) is applied to the sources of the PMOS1 and the PMOS2, and the PMOS1 and the PMOS2 form a current mirror circuit. First and second switching elements and a first constant-current source are connected to the drain of the PMOS2. A connection point (a node) of the first switching element and the second switching element is connected to an output terminal. The drain of the PMOS1 is connected to the first constant-current source through a third switching element, and connected to a second constant-current source through a fourth switching element.

Abstract: A combined AD/DA converting apparatus carrying out AD conversion of an analog input signal to output a converted digital signal or carrying out DA conversion of a digital input signal to output a converted analog signal based on a conversion selection signal for selecting AD conversion or DA conversion comprises an input signal selection circuit configured to select one analog signal out of a plurality of analog input signals to be output based on an input selection signal; an input sample hold circuit configured to sample and hold the analog input signal output from the input signal selection circuit; a DA converter configured to convert a digital signal into an analog signal to be output; a comparator circuit configured to output a comparison signal that indicates a size relation between the analog input signal output from the input sample hold circuit and the analog signal output from the DA converter; a sequential comparison register configured to define sequentially each place of a digital signal stored