Patents by Inventor Taiji OGAWA
Taiji OGAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9795027Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31) formed on the insulating substrate (10); a second signal line (L32) having a shorter length than that of the first signal line (L31); and a ground layer (30) formed for the first signal line (L31) and the second signal line (L31) via an insulating material (10). The ground layer (30) includes a first ground layer (G31) corresponding to a first region (D1) and a second ground layer (G32) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31) and has a first predetermined width (W31). The second region (D2) is defined based on the second signal line (L32) and has a second predetermined width (W32). The first ground layer (G31) has a remaining ratio lower than a remaining ratio of the second ground layer (G32).Type: GrantFiled: May 20, 2015Date of Patent: October 17, 2017Assignee: FUJIKURA LTD.Inventors: Hirohito Watanabe, Taiji Ogawa
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Patent number: 9549460Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31A) that constitutes differential signal lines formed on the insulating substrate (10) and includes a curved portion; a second signal line (L31B) provided along the first signal line (L31A) and side by side inside the curved portion; and a ground layer (30) formed for the first signal line (L31A) and the second signal line (L31B) via an insulating material (10). The ground layer (30) includes a first ground layer (G31A) corresponding to a first region (D1) and a second ground layer (G31B) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31A) and has a first predetermined width (W31A). The second region (D2) is defined based on the second signal line (L31B) and has a second predetermined width (W31B).Type: GrantFiled: May 20, 2015Date of Patent: January 17, 2017Assignee: FUJIKURA LTD.Inventors: Hirohito Watanabe, Taiji Ogawa
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Publication number: 20150342030Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31A) that constitutes differential signal lines formed on the insulating substrate (10) and includes a curved portion; a second signal line (L31B) provided along the first signal line (L31A) and side by side inside the curved portion; and a ground layer (30) formed for the first signal line (L31A) and the second signal line (L31B) via an insulating material (10). The ground layer (30) includes a first ground layer (G31A) corresponding to a first region (D1) and a second ground layer (G31B) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31A) and has a first predetermined width (W31A). The second region (D2) is defined based on the second signal line (L31B) and has a second predetermined width (W31B).Type: ApplicationFiled: May 20, 2015Publication date: November 26, 2015Applicant: FUJIKURA LTD.Inventors: Hirohito WATANABE, Taiji OGAWA
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Publication number: 20150340751Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31) formed on the insulating substrate (10); a second signal line (L32) having a shorter length than that of the first signal line (L31); and a ground layer (30) formed for the first signal line (L31) and the second signal line (L31) via an insulating material (10). The ground layer (30) includes a first ground layer (G31) corresponding to a first region (D1) and a second ground layer (G32) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31) and has a first predetermined width (W31). The second region (D2) is defined based on the second signal line (L32) and has a second predetermined width (W32). The first ground layer (G31) has a remaining ratio lower than a remaining ratio of the second ground layer (G32).Type: ApplicationFiled: May 20, 2015Publication date: November 26, 2015Applicant: FUJIKURA LTD.Inventors: Hirohito WATANABE, Taiji OGAWA
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Patent number: 8841976Abstract: The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.Type: GrantFiled: January 9, 2012Date of Patent: September 23, 2014Assignee: Fujikura Ltd.Inventors: Taiji Ogawa, Hirohito Watanabe, Masazaku Sato
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Patent number: 8574449Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.Type: GrantFiled: May 2, 2012Date of Patent: November 5, 2013Assignee: Fujikura Ltd.Inventors: Hirohito Watanabe, Taiji Ogawa, Eriko Tomonaga
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Publication number: 20120279050Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.Type: ApplicationFiled: May 2, 2012Publication date: November 8, 2012Applicant: FUJIKURA LTD.Inventors: Hirohito WATANABE, Taiji OGAWA, Takaomi Tomonaga, Eriko TOMONAGA
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Publication number: 20120205141Abstract: The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.Type: ApplicationFiled: January 9, 2012Publication date: August 16, 2012Applicant: FUJIKURA LTD.Inventors: Taiji OGAWA, Hirohito WATANABE, Masakazu SATO
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Publication number: 20120175158Abstract: A circuit board 1 comprises: an insulating substrate 10; and electric circuit patterns 20 formed on the insulating substrate 10. Each electric circuit pattern 20 has: a mounting pad section 30; and a wiring section 40 extending from the mounting pad section 30. The mounting pad section 30 has a first nonparallel surface 32a inclined to or substantially orthogonally intersecting a main surface 41 of the wiring section 40.Type: ApplicationFiled: March 22, 2012Publication date: July 12, 2012Applicant: FUJIKURA LTD.Inventor: Taiji OGAWA