Abstract: An integrated circuit such as a host adapter for connection to a system bus of a host computer includes a memory interface for a local memory including a serial memory such as an SEEPROM. The memory interface is capable of unsupervised multi-bit transfers between the serial memory and a data register in the memory interface. The host computer to access the serial memory starts the memory interface on a multi-bit access (i.e., read, write, or erase), checks a busy bit in the memory interface to determine when the access is complete, and accesses the data register. Thus, the host computer is decoupled from bit-by-bit management of transfers, and the integrated circuit or a bus device incorporating the integrated circuit requires less software overhead for use of serial memory. The memory interface further includes protection circuitry that prevents writing or erasing of a portion of the memory that a flag designates as protected.