Patents by Inventor Taiki HASHIGUCHI
Taiki HASHIGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11056601Abstract: A solar cell includes an n-type silicon substrate having a first main surface and a second main surface, an n-type first semiconductor layer disposed above the first main surface, a first intrinsic semiconductor layer disposed between the first main surface and the first semiconductor layer, a p-type second semiconductor layer disposed on the second main surface, and a second intrinsic semiconductor layer disposed between the second main surface and the second semiconductor layer. An oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer is lower than an oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer. An oxygen concentration at an interface between the second intrinsic semiconductor layer and the second semiconductor layer is higher than an oxygen concentration at an interface between the first intrinsic semiconductor layer and the first semiconductor layer.Type: GrantFiled: September 10, 2019Date of Patent: July 6, 2021Assignee: PANASONIC CORPORATIONInventors: Taiki Hashiguchi, Kenta Matsuyama
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Publication number: 20200111928Abstract: A solar cell includes an n-type silicon substrate having a first main surface and a second main surface, an n-type first semiconductor layer disposed above the first main surface, a first intrinsic semiconductor layer disposed between the first main surface and the first semiconductor layer, a p-type second semiconductor layer disposed on the second main surface, and a second intrinsic semiconductor layer disposed between the second main surface and the second semiconductor layer. An oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer is lower than an oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer. An oxygen concentration at an interface between the second intrinsic semiconductor layer and the second semiconductor layer is higher than an oxygen concentration at an interface between the first intrinsic semiconductor layer and the first semiconductor layer.Type: ApplicationFiled: September 10, 2019Publication date: April 9, 2020Inventors: Taiki HASHIGUCHI, Kenta MATSUYAMA
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Patent number: 9570637Abstract: A solar cell includes: a semiconductor substrate having a light receiving surface and a back surface; a first semiconductor layer of the first conductivity type on the back surface; a second semiconductor layer of the second conductivity type on the back surface; a first electrode electrically connected to the first semiconductor layer; and an insulating layer for electrically insulating the first semiconductor layer and the second semiconductor layer from each other in a region in which an edge of the first semiconductor layer and an edge of second semiconductor layer overlap. The first electrode includes a first transparent electrode layer and a first collection electrode layer on the first transparent electrode layer. The first transparent electrode layer is separated into a primary electrode layer that is on the first semiconductor layer and a separated electrode layer that is on the second semiconductor layer in the region.Type: GrantFiled: July 26, 2016Date of Patent: February 14, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Naoteru Matsubara, Taiki Hashiguchi
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Publication number: 20160336463Abstract: A solar cell includes: a semiconductor substrate having a light receiving surface and a back surface; a first semiconductor layer of the first conductivity type on the back surface; a second semiconductor layer of the second conductivity type on the back surface; a first electrode electrically connected to the first semiconductor layer; and an insulating layer for electrically insulating the first semiconductor layer and the second semiconductor layer from each other in a region in which an edge of the first semiconductor layer and an edge of second semiconductor layer overlap. The first electrode includes a first transparent electrode layer and a first collection electrode layer on the first transparent electrode layer. The first transparent electrode layer is separated into a primary electrode layer that is on the first semiconductor layer and a separated electrode layer that is on the second semiconductor layer in the region.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Naoteru MATSUBARA, Taiki HASHIGUCHI
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Publication number: 20160093754Abstract: A solar cell includes: a semiconductor substrate of one conductivity type; a first semiconductor layer of the one conductivity type on the semiconductor substrate; a second semiconductor layer of the other conductivity type on the semiconductor substrate; an insulation layer between the first and second semiconductor layers in an area where the first and second semiconductor layers layer overlap each other; a first region where the first semiconductor layer is joined to the semiconductor substrate; a second region where the second semiconductor layer is joined to the semiconductor substrate; and a third region, which is a part of the first region, where the insulation layer is provided. The first region includes first finger sections and a first busbar section. The second region includes second finger sections and a second busbar section. At least a part of the first busbar section is provided in the third region.Type: ApplicationFiled: September 24, 2015Publication date: March 31, 2016Inventors: Tsuyoshi TAKAHAMA, Naofumi HAYASHI, Taiki HASHIGUCHI, Akimichi MAEKAWA
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Patent number: 9257593Abstract: There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer (16) and an n-type amorphous silicon layer (14) are formed over a light-receiving surface of an n-type monocrystalline silicon substrate (18); a second step in which an i-type amorphous silicon layer (22a) and an n-type amorphous silicon layer (23a) are formed over a back surface of the n-type monocrystalline silicon substrate (18); and a third step in which, after the first step and the second step are completed, protection layers are formed over the n-type amorphous silicon layer (14) and the n-type amorphous silicon layer (23a).Type: GrantFiled: September 17, 2013Date of Patent: February 9, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Taiki Hashiguchi, Yutaka Kirihata
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Patent number: 9070822Abstract: The method disclosed herein includes a first step of forming an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 on a light-receiving surface of an n-type monocrystalline silicon substrate 18; a second step of forming an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a on a backside surface of the n-type monocrystalline silicon substrate 18; and a third step of forming, after completion of the first step and the second step, an antireflection layer 12 on the n-type amorphous silicon layer 14, and subsequently forming an insulating layer 24a on the n-type amorphous silicon layer 23a.Type: GrantFiled: September 25, 2013Date of Patent: June 30, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yutaka Kirihata, Taiki Hashiguchi
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Patent number: 8877545Abstract: A manufacturing includes forming an insulating layer covering a portion of a first semiconductor layer on a semiconductor substrate, removing a portion of the first semiconductor layer which is not covered with the insulating layer with an etchant to expose a potion of the first main surface, and cleaning the first main surface using a cleaning liquid containing hydrofluoric acid. An etching rate by the etchant to etch the first semiconductor layer is higher than an etching rate by the etchant to etch a first surface layer of the insulating layer, the first surface layer being on the side opposite to the first semiconductor layer. An etching rate by the cleaning liquid to etch a second surface layer of the insulating layer, the second surface layer being on the first semiconductor layer side, is lower than an etching rate by the cleaning liquid to etch the first surface layer.Type: GrantFiled: January 29, 2013Date of Patent: November 4, 2014Assignee: Sanyo Electric Co., Ltd.Inventors: Masato Shigematsu, Koichi Kubo, Takahiro Mishima, Yasuko Hirayama, Taiki Hashiguchi
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Publication number: 20140024167Abstract: The method disclosed herein includes a first step of forming an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 on a light-receiving surface of an n-type monocrystalline silicon substrate 18; a second step of forming an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a on a backside surface of the n-type monocrystalline silicon substrate 18; and a third step of forming, after completion of the first step and the second step, an antireflection layer 12 on the n-type amorphous silicon layer 14, and subsequently forming an insulating layer 24a on the n-type amorphous silicon layer 23a.Type: ApplicationFiled: September 25, 2013Publication date: January 23, 2014Applicant: SANYO Electric Co., Ltd.Inventors: Yutaka KIRIHATA, Taiki HASHIGUCHI
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Publication number: 20140020756Abstract: A photovoltaic device (10) is provided with: an n-type monocrystalline silicon substrate (21); an IN layer (25) layered over one surface of the n-type monocrystalline silicon substrate (21); an IP layer (26) layered over a region, of one surface of the IN layer 25, where the IN layer (25) is not layered, and layered so as to have an overlap region (26*) which is overlapped with the region where the IN layer (25) is layered; an n-side electrode (40) electrically connected to the IN layer (25) and formed over the overlap region (26*); and a p-side electrode (50) formed distanced from the n-side electrode (40) and electrically connected to the IP layer (26). In the IP layer (26), a separation gap (60) is formed between a region where the n-side electrode (40) is formed and a region where the p-side electrode (50) is formed.Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: SANYO Electric Co., Ltd.Inventors: Ryo GOTO, Taiki HASHIGUCHI, Kazunori FUJITA, Masato SHIGEMATSU, Yutaka KIRIHATA, Takahiro MISHIMA
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Publication number: 20140017850Abstract: There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer (16) and an n-type amorphous silicon layer (14) are formed over a light-receiving surface of an n-type monocrystalline silicon substrate (18); a second step in which an i-type amorphous silicon layer (22a) and an n-type amorphous silicon layer (23a) are formed over a back surface of the n-type monocrystalline silicon substrate (18); and a third step in which, after the first step and the second step are completed, protection layers are formed over the n-type amorphous silicon layer (14) and the n-type amorphous silicon layer (23a).Type: ApplicationFiled: September 17, 2013Publication date: January 16, 2014Applicant: SANYO Electric Co., Ltd.Inventors: Taiki HASHIGUCHI, Yutaka KIRIHATA