Abstract: A clock signal is frequency divide to generate a plurality of signals CK, CK′ having different periods, and a plurality of the control signals C, TZS are generated from them. One of the control signals C, TZS is selected as control signal TZ1, depending on the comparison section T1-T4, so as to change the period of the control signal for each comparison section. The reference voltage and the input voltage are compared according to the control signal TZ1. The period of the control signal is made shorter at the comparison sections other than the section T2 which requires a longer comparison time for the stabilization of the reference voltage, due to the large difference of the former reference voltage and the present reference voltage.

Abstract: A pulse width determining device includes a down counter for counting down from a first initial count value reloaded thereinto. If the down counter underflows, it can start counting down from a second initial count value reloaded thereinto as needed. Every time the device receives an input pulse, a count clock control circuit can set a period of time during which it can generate and furnish count clock pulses to the down counter, according to the pulse width of the input pulse. The device can determine whether or not the pulse width of the input pulse is in a predetermined range of pulse widths according to a relation between timing with which the down counter underflows and the time period during which the count clock pulses are generated.

Abstract: A constant voltage generation circuit in which a charging circuit (T1) connected to one side of resistors (LR2 to LR5) rapidly supplies a higher voltage, that is further higher than any voltage generated at each of the resistors (LR2 to LR5), to the output terminal (OT) during a desired time period when one of switches (SW2 to SW4) turns on to provide the voltage to be switched to the output terminal (OT) and when the voltage to be switched is higher than a current voltage of the output terminal (OT). Furthermore, in the circuit, a charging circuit (T2 ) connected to other side of resistors (LR2 to LR5) rapidly supplies a lower voltage, that is further lower than any voltage generated at each of the resistors (LR2 to LR5), to the output terminal (OT) during a desired time period when one of switches (SW2 to SW4) turns on to provide the voltage to be switched to the output terminal (OT) and when the voltage to be switched is lower than a current voltage of the output terminal (OT).

Abstract: A method of controlling an analog-to-digital (A/D) converter for converting an input voltage into digital data. The conversion process includes charging a capacitor with the input voltage to be converted into a digital data, and disconnecting the input voltage from the capacitor. A reference voltage, generated according to digital data, is furnished by a control circuit to a digital-to-analog (D/A) converting unit. The reference voltage is applied to the capacitor by turning on a switch connected between the D/A converting unit and the capacitor. New digital data to be furnished by the control circuit is determined according to a charged voltage on the capacitor. The D/A converting unit causes the reference voltage to be delivered to the capacitor to change to a new value according to the new digital data from the control circuit.

Abstract: A motor control apparatus which comprises: a central processing unit which executes general control of processing of the motor control apparatus, a timer portion which generates predetermined pulses from a reference clock signal, a plurality of registers provided corresponding to control signals of respective phases in which data can be reloaded by the central processing unit, shift registers which are able to store the data having the same number of bits as the number of the registers and the values of plurality of registers can be reloaded to the shift registers by the predetermined pulses output from the timer portion, and a control signal generator means which generates control signals of respective phases of a polyphase motor.