Patents by Inventor Tai-Min Chang
Tai-Min Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990383Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.Type: GrantFiled: November 2, 2022Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
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Publication number: 20230411496Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.Type: ApplicationFiled: May 23, 2022Publication date: December 21, 2023Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Yi-Ning TAI, Hong-Mao LEE, Yan-Ming TSAI, Wei-Yip LOH, Harry CHIEN, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
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Patent number: 11848233Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.Type: GrantFiled: March 27, 2022Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
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Publication number: 20230384684Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.Type: ApplicationFiled: July 25, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
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Patent number: 11823969Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: GrantFiled: June 30, 2022Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20230369153Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20230352442Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11789366Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.Type: GrantFiled: June 1, 2022Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
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Patent number: 11742317Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: October 17, 2019Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230137108Abstract: Techniques described herein include performing a first anneal operation on a first portion of the interconnect, filling the remaining portion of the interconnect, and then performing a second anneal operation on the interconnect. The two-step anneal techniques described herein enable the removal of defects in an interconnect structure, particularly for high aspect ratio interconnect structures. Accordingly, the two-step anneal techniques described herein may be used to fabricate defect free or near defect free interconnect structures in a semiconductor device. This reduces contact resistance for the interconnect structures, reduces premature device failure for the semiconductor device, increases manufacturing yield, and increases tolerance of the interconnect structures to subsequent processing operations, among other examples.Type: ApplicationFiled: January 6, 2022Publication date: May 4, 2023Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
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Publication number: 20230054148Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.Type: ApplicationFiled: November 2, 2022Publication date: February 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
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Patent number: 11587902Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: September 19, 2019Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230048907Abstract: An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, dummy posts, and a protection layer. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads and are electrically floating. The protection layer covers the conductive posts and the dummy posts. A distance between top surfaces of the conductive posts and a top surface of the protection layer is smaller than a distance between top surfaces of the dummy posts and the top surface of the protection layer.Type: ApplicationFiled: November 1, 2022Publication date: February 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
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Publication number: 20230036693Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.Type: ApplicationFiled: February 18, 2022Publication date: February 2, 2023Inventors: Kan-Ju Lin, Chien Chang, Chih-Shiun Chou, Tai Min Chang, Yi-Ning Tai, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Lin-Yu Huang
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Publication number: 20230008239Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.Type: ApplicationFiled: April 12, 2022Publication date: January 12, 2023Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
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Patent number: 11515276Abstract: An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, and dummy posts. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads. A height of the conductive posts is greater than a height of the dummy posts.Type: GrantFiled: August 30, 2020Date of Patent: November 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
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Patent number: 11515224Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: GrantFiled: January 17, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Patent number: 11508633Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.Type: GrantFiled: May 28, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
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Publication number: 20220336307Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20220299880Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.Type: ApplicationFiled: June 1, 2022Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang