Abstract: The present disclosure discloses a display driving apparatus in which the consumption power of a chip is optimized through control for each output channel of the chip. The display driving apparatus includes a consumption current control circuit for each output channel. The consumption current control circuit is configured to selectively provide a control current having a high current amount in order to drive an output voltage for the output side of an output buffer in response to a change in the pattern having a great difference between an input voltage and an output voltage.

Abstract: Disclosed is an output buffer circuit for a display driving apparatus, which generates an output voltage by using a bias current controlled by digital-to-analog conversion for interpolation data, the output buffer circuit including a decoder configured to output control data obtained by decoding interpolation data, and an output circuit configured to output an output voltage by using a bias current having the amount of current controlled by digital-to-analog conversion for the control data.

Abstract: The present disclosure discloses a display driving apparatus configured to process data by using a low voltage bias current, process a source signal by using a high voltage bias current, and provide the low voltage bias current and the high voltage bias current by using one bias core.

Abstract: The present disclosure discloses a source signal output circuit and an inverter thereof. The inverter is configured to provide a multiplexer with a control signal having a full range for selecting a source signal and to output the control signal having the full range by using elements operating in a low voltage range. Therefore, the present disclosure has an advantage in that it can fabricate a driving circuit having a small area at a low process cost.

Abstract: The present disclosure relates to a technology for adjusting differences among integrated circuits, that may occur in a pixel sensing, using bias voltages, and more particularly, a technology for adjusting a gain or an offset of each integrated circuit by adjusting a bias voltage.

Abstract: The present disclosure provides, in a pixel sensing, a technology in which a parasitic impedance formed in a sensing line does not affect an integrating circuit using a current mirror circuit coupled with an operational amplifier.

Abstract: An embodiment is disclosed that makes it possible to reduce the area of a digital-to-analog converter circuit by interpolating one reference voltage and generating a plurality of gamma voltages.

Abstract: A display driving apparatus includes a first bias circuit configured to provide a first bias current; a second bias circuit configured to provide a second bias current; a selection circuit configured to select and output the first bias current as a bias current during a first period in which a change in a driving current occurs, and select and output the second bias current as the bias current during a second period from after the first period to until a next change in the driving current occurs; and an output buffer configured to drive a first input current or a second input current by the bias current, and output the driving current for driving a panel, in correspondence to the first input current or the second input current.

Abstract: Disclosed is a display driving device capable of reducing an output response delay of an output buffer. The display driving device may include: a first DAC configured to load a first grayscale voltage corresponding to first digital data as a first DAC signal; a second DAC configured to load a second grayscale voltage corresponding to second digital data as a second DAC signal; and an output buffer configured to alternately select the first DAC signal loaded to a first input terminal and the second DAC signal loaded to a second input terminal.

Abstract: Disclosed is a display driving device capable of reducing an output response delay of an output buffer. The display driving device may include: a first DAC configured to load a first grayscale voltage corresponding to first digital data as a first DAC signal; a second DAC configured to load a second grayscale voltage corresponding to second digital data as a second DAC signal; and an output buffer configured to alternately select the first DAC signal loaded to a first input terminal and the second DAC signal loaded to a second input terminal.