Abstract: A method for data breach protection includes identifying data partners of an enterprise and determining data usage policies of the data partners. The data usage policies of the data partners may be monitored and a change in at least one data usage policy of at least one data partner may be detected. A similarity between an original version of the at least one data usage policy and the changed version of the at least one data usage policy may be determined. Results of the determined similarity may be displayed.

Abstract: According to some embodiments, a method is performed by an augmented reality (AR) device. The AR device comprises a display configured to overlay virtual objects onto a field of view of a user in real-time. The method comprises: establishing an audio-video connection between a first user and a second user; receiving an indication from an AR engine that an AR model from the first user is available to the second user; retrieving the AR model from the AR engine, wherein the AR model represents a real world object in the field of view of the second user; determining a surface in the field of view of the second user for projection of the AR model; and displaying on the determined surface an AR projection based on the AR model to the second user via the display.

Abstract: A method for data breach protection includes analyzing network traffic of an enterprise. Uniform Resource Locators (URLs) included in the network traffic may be identified. The URLs may be classified into a bipartite graph. Classification sets of the bipartite graph may be established and displayed. In response to displaying the classification sets, an instruction related to management of the network traffic may be received and/or executed.

Abstract: A method for telemetry analysis of a digital twin includes analyzing network traffic sent or received by a host network. Entities exchanging data with the host network are identified. A plurality of applications within the host network used for sending or receiving the exchanged data may be identified. A digital twin of the host network is developed based upon the identified entities exchanging data with the host network and the applications within the host network used for sending or receiving the exchanged data. Stimuli may be applied to the digital twin, and the likelihood of a change in state within the host network is assessed based upon the applied stimuli.

Abstract: According to some embodiments, a method is performed by an augmented reality (AR) device. The AR device comprises a display configured to overlay virtual objects onto a field of view of a user in real-time. The method comprises receiving an indication from an e-commerce engine that an AR model is available to the user, wherein the AR model represents an e-commerce product and comprises attributes describing the e-commerce product, and retrieving the AR model from the e-commerce engine. The AR model represents a product offered by the e-commerce engine (e.g., gift card, coupon code, offer code). The method further comprises determining a surface in the field of view of the second user for projection of the AR model and displaying on the determined surface an AR projection based on the AR model to the user via the display. The AR projection represents the product represented by the AR model.

Abstract: A method predicting risk includes identifying data partners associated with the enterprise and generating a computer readable model of the enterprise including representations of digital and physical assets, and data partners. Risk analysis algorithms may be applied to the computer readable model. A risk model associated with risk analysis may be generated, using the computer readable model, and results of the risk model may be displayed at a user interface.

Abstract: A method and apparatus for providing memory patching in a data process system (5). In one embodiment, access control register (32), found in protection registers (20), contains six fields corresponding to six blocks of memory within the ROM (14). Each field includes a patch protect bit (36 and 42) as well as other access protect bits such as read protect and execute protect. The access control unit (28) selectively outputs an access error to the CPU (10) based on the state of the protect bits corresponding to the block of memory being accessed. The patch protect bit, by way of a force patch exception signal (19), alerts the CPU (10) whether the corresponding block of ROM (14) requires a patch. If a patch is required, the maskable address comparator (50) defines the size of the memory patch where the size of the patch can range from a single address location to multiple lines or blocks of contiguous memory.

Abstract: A data processing system (10) which detects unauthorized memory accesses has trap door logic (17) that receives memory address bus (16) signals from a processor (12). The trap door logic (12) utilizes address detection logic (50, 52) to identify page numbers utilizing high order address bits and trap regions utilizing low order address bits. The resulting page number (70-76) signals and trap region (41-44) signals are selectively combined (54) to generate an exception signal (18) which is received by security logic (19). The selective combination (54) may be programmed, or may be fixed during fabrication. In response to the exception signal (18), the security logic (19) implements a predefined security policy, which is transmitted to the processor (12) over control lines (20).

Abstract: A data processor (20) includes a firewall circuit (50) that monitors privilege level changes or transitions between privilege modes, such as from user mode and user space into supervisory or privileged mode and operating system space. The firewall circuit starts a timer (54) whenever a central processing unit (22) enters supervisor mode. If the timer (54) determines the passage of a predetermined time while the central processing unit remains continuously in supervisory mode without re-entering user mode, a predefined security policy is invoked. For example, the security policy may require at this point that the data processor (20) is to be reset. Different timer (54) time-out values and different security policies can be set for different types of privilege level changes. In one embodiment, a default time-out value provides protection for multiple types of privilege level changes.

Abstract: A data processing system (10) having an access protect unit (20) for tracing memory accesses. A trace bit (50) is associated with each page of memory and when set generates an interrupt signal on a first valid access to the page. The access protect unit (20) supports trace in both supervisor and user mode without the need for an emulation system or an on-chip emulator. Tracing is done without providing "backdoor" access to the central processing unit (CPU). The access protect unit (20) allows programmable memory segment tracing. Signature monitoring of memory accesses is accomplished by storing sequential memory segments in a plurality of registers.

Abstract: A method and apparatus for providing access protection in an integrated circuit (10). In one embodiment access protection circuitry (11) includes access attribute bits (51) which are compared to the access attributes (68) of a memory (14) request. If a mismatch occurs, an access fault signal (52) is asserted. If access fault signal (52) is asserted and a selective reset bit (48) has selected a first memory protection mode, then signal generation circuitry (44) asserts a reset signal (58). Reset signal (58) may be used to initiate a hardware reset of data processor (10). If access fault signal (52) is asserted and a selective reset bit (48) has selected a second memory protection mode, then signal generation circuitry (44) asserts an exception occurred signal (60).