Abstract: A MOS transistor cell is disclosed for a multiple cell MOS transistor, such as in an ESD protection circuit, output buffer, etc. The transistor cell has a regular n-sided polygonal geometry, wherein n.gtoreq.8. A drain region is provided in a substrate which occupies an area with n-sided polygonal shaped boundaries. Surrounding the drain, is a channel region which occupies an n-sided polygonal shaped area. Surrounding the channel region is a source region provided in the substrate which occupies an annular shaped area having n-sided polygonal boundaries.

Abstract: An output buffer is provided which receives an input signal for output onto an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage corresponding to a logic value of the input signal. The second driver has a higher driving capacity than the first driver. The output buffer also has control circuitry receiving a transition in logic value of the input signal and at least one mode signal. The control circuitry responds to the transition in logic value by delaying the second driver from driving the output terminal to a complementary voltage until after the first driver begins to drive the output terminal to the complementary voltage. In so doing, the control circuitry delays the second driver by a first delay, when the mode signal(s) indicates a full speed mode. On the other hand, the control circuitry delays the second driver by a second delay, that is longer than the first delay, when the mode signal(s) indicates a low speed mode.

Abstract: A low power consumption oscillator circuit is provided with an oscillator. The oscillator responds to a voltage by producing an oscillating signal at its output having an amplitude that depends on the level of the voltage. Furthermore, the low power consumption oscillator circuit has a level shifter. Illustratively, according to one embodiment, the level shifter includes a pull-up driver and a pull-down driver connected in parallel between the oscillator output and an output of the level shifter. The pull-up driver is configured so as to refrain from conducting current between a biasing input of the pull-up driver and the level shifter output simultaneously with the pull-down driver when the oscillating signal exceeds a certain voltage level. The level shifter illustratively includes an intrinsic PMOS device.

Abstract: An ESD protection circuit for use in a CMOS output buffer circuit has been disclosed. The ESD protection circuit provides a high ESD failure threshold in a small layout area to protect the output buffer against ESD failure. The output buffer includes a pull-up PMOS device and pull-down NMOS device whose common drain is connected to an output pad. The source of the PMOS device is connected to VDD and the source of NMOS device is connected to VSS. The ESD protection circuit is formed by a PTLSCR device and an NTLSCR device. The PTLSCR (NTLSCR) is formed by inserting a short-channel thin-oxide PMOS (NMOS) device into a lateral SCR structure. These MOS devices reduce the turn-on voltage of the lateral SCR to the snapback breakdown voltage of the MOS rather than the original switching voltage of the SCR. The ESD protection circuit also includes two parasitic diodes D.sub.p between output pad and VDD and D.sub.n between output pad and VSS.

Abstract: An ESD protection circuit fully protects the input stage of CMOS integrated circuits from four different ESD stress modes by providing four different ESD direct discharging paths. The ESD protection circuit has a primary ESD protection circuit, which has a first and a second thick-oxide MOS devices, and a secondary ESD protection circuit which has a resistor, a first and a second thin-oxide MOS devices. The resistor is connected between the primary and secondary ESD protection circuits. The primary and secondary ESD protection circuits each provide two ESD discharge paths from the input pad, and from the input of the internal circuits to be protected, to VDD and VSS voltage supply buses. The inventive ESD protection circuit also has merged latchup guard rings and protects against large ESDs, while occupying only a small layout area. Furthermore, the inventive ESD protection circuit clamps the voltage level of the input signal between 5.

Abstract: An on-chip ESD protection circuit for use in a submicron CMOS integrated circuit (IC) has been disclosed. The ESD protection circuit provides a high ESD failure threshold in a small layout area to protect the input stage of the submicron CMOS IC against ESD failure. The ESD protection circuit is formed by a PTLSCR1, PTLSCR2 devices and an NTLSCR1, NTLSCR2 devices. The PTLSCR1 or PTLSCR2 (NTLSCR1 or NTLSCR2) is formed by inserting a short-channel thin-oxide PMOS (NMOS) device into the lateral SCR structure. These MOS devices are used to reduce the turn-on voltage of the lateral SCR to below the gate-oxide breakdown voltage of the CMOS devices in the input stage. Thus these PTLSCR1, PTLSCR2, NTLSCR1 and NTLSCR2 devices perform full ESD protection without additional secondary ESD protection elements. The four modes of ESD, PS, NS, PD and ND, are one-by-one protected by the NTLSCR1, NTLSCR2, PTLSCR1 and PTLSCR2 devices respectively.