Abstract: A semiconductor device includes a reference voltage generation circuit, an amplifier circuit, and a voltage dropping circuit. The reference voltage generation circuit includes a negative feedback circuit to generate a reference voltage controlled by an output signal from the negative feedback circuit. The amplifier circuit amplifies the output signal from the negative feedback circuit at the leading edge of an external power supply voltage or the input time of an external signal. The voltage dropping circuit drops the external power supply voltage in accordance with the reference voltage output from the reference voltage generation circuit to generate an internal power supply voltage.

Abstract: A semiconductor device includes a first detection circuit, a second detection circuit, a determination circuit and a pulse generation circuit. The first detection circuit detects the leading edge of the pulse waveform of an input signal. The second detection circuit detects the trailing edge of the pulse waveform of the input signal. The determination circuit determines whether the pulse width of the pulse waveform is shorter than a given period, based on detection results of the first detection circuit and the second detection circuit. The pulse generation circuit generates a pulse signal when the determination circuit determines that the pulse width of the pulse waveform is shorter than the given period.

Abstract: A semiconductor device includes a reference voltage generation circuit, an amplifier circuit, and a voltage dropping circuit. The reference voltage generation circuit includes a negative feedback circuit to generate a reference voltage controlled by an output signal from the negative feedback circuit. The amplifier circuit amplifies the output signal from the negative feedback circuit at the leading edge of an external power supply voltage or the input time of an external signal. The voltage dropping circuit drops the external power supply voltage in accordance with the reference voltage output from the reference voltage generation circuit to generate an internal power supply voltage.

Abstract: A semiconductor device includes a first detection circuit, a second detection circuit, a determination circuit and a pulse generation circuit. The first detection circuit detects the leading edge of the pulse waveform of an input signal. The second detection circuit detects the trailing edge of the pulse waveform of the input signal. The determination circuit determines whether the pulse width of the pulse waveform is shorter than a given period, based on detection results of the first detection circuit and the second detection circuit. The pulse generation circuit generates a pulse signal when the determination circuit determines that the pulse width of the pulse waveform is shorter than the given period.

Abstract: A semiconductor device comprises a high-voltage detector for generating a test mode signal and a detection signal when a test mode setting signal is inputted from an input terminal for inputting, as a first input signal, any one of a normal signal and the test mode setting signal having a higher voltage than the normal signal, an input circuit for generating a normal mode signal in accordance with the normal signal, and a protection circuit for reducing an electric field between an input side and a low-voltage power supply side of the input circuit in accordance with the detection signal, the electric field being generated by inputting the test mode setting signal thereto.

Abstract: A semiconductor device comprises a high-voltage detector for generating a test mode signal and a detection signal when a test mode setting signal is inputted from an input terminal for inputting, as a first input signal, any one of a normal signal and the test mode setting signal having a higher voltage than the normal signal, an input circuit for generating a normal mode signal in accordance with the normal signal, and a protection circuit for reducing an electric field between an input side and a low-voltage power supply side of the input circuit in accordance with the detection signal, the electric field being generated by inputting the test mode setting signal thereto.

Abstract: According to a first aspect of the present invention, there is provided a method of correcting a mask for a data program of a read only memory, comprising selecting an optional data from a data map comprising first data and second data, the optional data being one of the first data, and inspecting neighboring data around the optional data and, where all the neighboring data surrounding the optional data are the second data, correcting a shape of the mask in a position corresponding to the optional data.

Abstract: The semiconductor memory device comprises a plurality of data output terminals outputting in parallel data of a plurality of bits, the number of bits being a plurality of times as large as the number of the plurality of data output terminals, an address transition detecting circuit to output a latch control signal, and an output control circuit for performing a switching control on the basis of a switching signal such that the data read in parallel in each read cycle is held by a latch circuit, and the data held by the latch circuit is divided by a plural number and one group of the divided data is outputted to the plurality of data output terminals during the cycle, with the remaining group of divided data being outputted to the plurality of data output terminals during the next read cycle.

Abstract: A semiconductor memory device includes a memory cell array from or to which data is read or written, an identification circuit to identify a particular signal which allows a particular operation that is not part of normal operations to read or write data from or to the memory cell array to be performed on the memory cell array, and a control circuit which performs the particular operation on the memory cell array when the particular signal is identified by the identification circuit.

Abstract: A semiconductor memory device includes a memory cell array from or to which data is read or written, an identification circuit to identify a particular signal which allows a particular operation that is not part of normal operations to read or write data from or to the memory cell array to be performed on the memory cell array, and a control circuit which performs the particular operation on the memory cell array when the particular signal is identified by the identification circuit.

Abstract: The semiconductor memory device comprises a plurality of data output terminals outputting in parallel data of a plurality of bits, the number of bits being a plurality of times as large as the number of the plurality of data output terminals, an address transition detecting circuit to output a latch control signal, and an output control circuit for performing a switching control on the basis of a switching signal such that the data read in parallel in each read cycle is held by a latch circuit, and the data held by the latch circuit is divided by a plural number and one group of the divided data is outputted to the plurality of data output terminals during the cycle, with the remaining group of divided data being outputted to the plurality of data output terminals during the next read cycle.

Abstract: According to a first aspect of the present invention, there is provided a method of correcting a mask for a data program of a read only memory, comprising selecting an optional data from a data map comprising first data and second data, the optional data being one of the first data, and inspecting neighboring data around the optional data and, where all the neighboring data surrounding the optional data are the second data, correcting a shape of the mask in a position corresponding to the optional data.

Abstract: A memory cell array is divided into a plurality of blocks and sense amplifiers and shift registers are provided for the respective blocks. After a plurality of data sets are read out in the first random access cycle and transferred to each of the shift registers, column switching is made and a plurality of next data sets are read out. Then, the pipeline processing for the data items is effected to serially read out data in the serial access cycle.

Abstract: An address storing PROM cell array formed of a PROM having one polysilicon layer stores an address of a defective cell contained in a mask ROM used as a main memory cell array. A data storing PROM cell array formed of a PROM having one polysilicon layer stores data to be written into the defective cell. When an input address hits the address stored in the address storing PROM cell array, an address detecting circuit reads out data stored in the data storing PROM cell array instead of data of the mask ROM. When data in an address corresponding to the defective cell of the mask ROM is rewritten twice or more, a priority setting circuit permits newest data to be preferentially read out.

Abstract: A decoder circuit comprises a plurality of input word select lines, a plurality of input block select lines, a main decoder, and a plurality of CMOS inverters each having a first power source node, a second power source node applied with a predetermined potential, an input node connected to one of the input word select lines, and a decoder output line. The main decoder activates/deactivates each CMOS inverter by applying an output signal to the first power source node of each CMOS inverter, thereby driving each decoder output line according to the logic level of the respective input word select line when the CMOS inverter is activated. The decoder circuit also includes means for controlling the logic level of the output block select lines according to the logic levels of the input block select lines.

Abstract: A method of manufacturing a double-layer gate programmable ROM is disclosed including the steps of: forming a plurality of first gate layers at predetermined intervals on a semiconductor substrate, source and drain regions being formed on the surface of the semiconductor substrate and under the first gate layers, respectively; forming a plurality of second gate layers between the first gate layers, channel regions being formed on the surface of the semiconductor substrate and under the second gate layers, respectively; and selectively implanting ions into the channel regions to program data.

Abstract: A mask read only memory (ROM) has a small chip size and realizes high-speed operation and a large capacity by reducing a wiring capacity of a main bit line and a virtual ground line.

Abstract: A mask ROM having a plurality of memory cell blocks, each composed of a main bit line, a ground line, and a plurality of memory cells for storing information. The mask ROM also includes a sense amplifier for reading the information stored in the memory cells via the main bit line. The mask ROM has a plurality of first block selecting means for selecting a memory cell block connected to the main bit line from a plurality of the memory cell blocks and a plurality of second block selecting means for selecting a memory cell block connected to the ground line from a plurality of the memory cell blocks. The first and second block selecting means are arranged alternately, with the memory cell block sandwiched therebetween.

Abstract: A semiconductor memory having a page mode includes a first circuit for reading out page data from a memory cell array, in accordance with cell address signals A3-A19, and a second circuit for latching, at the beginning of a page mode cycle, page data to be read out in the cycle, sequentially outputting the latched data in page address signals A0-A2, and inputting to the first circuit an address from which to read out page data to be output in a following page mode cycle. By provision of the first and second circuits, the period of time from a change in address to output of read-out data can be shortened considerably, permitting high-speed reading in the page mode.

Abstract: There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential.