Patents by Inventor Taira Matsunaga

Taira Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5238850
    Abstract: A Bi-MOS type semiconductor integrated circuit device having at least one bipolar transistor in an island region is provided. The island region is covered with a multilayer insulating film which is formed of a silicon oxide film and a silicon nitride film having a different etching resistance with each other. Collector and base contact holes and an intended emitter contact hole are formed in the multilayer insulating film at the same time to provide bipolar transistors having a fine structure. An insulated gate MOS transistor includes a protective film such as polysilicon film covering a gate insulating film to increase the reliability.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Matsunaga, Bunshiro Yamaki
  • Patent number: 5212398
    Abstract: In an integrated circuit device including a bipolar transistor, MOSFET, and protective diode for the MOSFET, all formed over a semiconductor substrate, the protective diode for holding an adequate electrostatic breakdown voltage for a gate oxide layer of the MOSFET is provided by forming a second conductivity type buried area continuous with, and in contact with, a second conductivity type region at a boundary between the first conductivity type semiconductor substrate and a first conductivity type second semiconductor layer. By doing so, a substantive junction depth Xj is made deeper as a whole with respect to the second conductivity type region. It is, therefore, possible to obtain a protective diode of adequate electrostatic breakdown-voltage characteristic which does not adversely affect the operation of the MOSFET even if a relatively thin semiconductor layer is employed.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: May 18, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Matsunaga, Bunshiro Yamaki
  • Patent number: 5115290
    Abstract: A MOS type semiconductor device and a method for the manufacture of the same are disclosed in which a gate electrode is so formed over a semiconductor substrate of a first conductivity type with a gate insulating film formed therebetween as to provide a three-layered structure composed of a first high melting point metal silicide layer formed on the gate insulating film, high melting point metal layer formed on the first high melting point metal silicide and a second high melting point metal silicide layer formed on the high melting point metal layer. In the gate electrode, a length of the first high melting point silicide layer defined in the same direction as that in which a channel region extends is made smaller in length than the high melting point metal layer.
    Type: Grant
    Filed: September 5, 1990
    Date of Patent: May 19, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouji Murakami, Taira Matsunaga
  • Patent number: 4928157
    Abstract: A protection diode structure for a MOS transistor which includes a semiconductor substrate layer and a gate electrode insulated from the semiconductor substrate layer and in which a driving voltage is applied therebetween to create an inversion layer in an operating mode, includes a first semiconductor layer, a second semiconductor layer formed in the first semiconductor layer and connected to the gate electrode, and a third semiconductor layer formed to surround the first semiconductor layer, uniformly separated from the second layer, and connected to the semiconductor substrate layer, wherein the first and second semiconductor layers constitute a first diode having a breakdown voltage greater than the driving voltage and less than the gate withstand voltage of the MOS transistor, and the first and third semiconductor layers constitute a second diode having a breakdown voltage less than the gate withstand voltage of the MOS transistor.
    Type: Grant
    Filed: April 5, 1989
    Date of Patent: May 22, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Matsunaga, Takashi Kimura
  • Patent number: 4757276
    Abstract: The signal-processing circuit of the present invention, more particularly the gain-controlled amplifier circuit, comprises a MOSFET (metal oxide semiconductor field-effect transistor), and an NPN bipolar transistor cascade-connected to the MOSFET. The gain-controlled amplifier circuit amplifiers the signal supplied to the gate of the MOSFET, with the gain corresponding to the voltage applied to the base of the NPN bipolar transistor. The circuit can generate an output signal at one end of the emitter-collector path of the NPN bipolar transistor, said output signal containing negligibly small distortion components; in particular, negligible third distortion components.
    Type: Grant
    Filed: August 25, 1986
    Date of Patent: July 12, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Ishii, Takashi Kimura, Taira Matsunaga, Mie Nomura, Shoichi Tanimata