Abstract: This application relates to compounds of Formula I: or pharmaceutically acceptable salts thereof, which are inhibitors of TAM kinases which are useful for the treatment of disorders such as cancer.

Abstract: A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use.

Abstract: A cache TAG RAM (20) has a TAG array (22, 24) for storing TAG addresses of data stored in a cache memory, and a valid bit array (26, 31). In the cache TAG RAM (20), a valid bit is set for each TAG address to indicate if the TAG address is valid. The valid bit array (26, 31) is located separate from the TAG array (22, 24). During power-up of the cache TAG RAM (20), a multiple step invalidation cycle is used to sequentially invalidate groups of columns of the valid bit array (26, 31). The multiple step invalidation cycle reduces the peak current during an invalidation cycle, thus reducing metal migration.

Abstract: An integrated circuit memory (20) has a write pulse generator (38) for generating a self-timed write pulse independent of system clock frequency and system clock duty cycle. The write pulse generator (38) includes a delay element (56) and a delay element (68). The write pulse is triggered on a rising edge of the clock signal and has a duration that is determined by a delay time provided by the delay element (68). The delay elements (56, 68) provide single-sided delays and compensate for process, power supply, temperature variations of the integrated circuit memory (20).

Abstract: A BICMOS output buffer circuit (20) has a voltage converter (21), a reference voltage circuit (28), a driver circuit (24), and a clamping circuit (40). The reference voltage circuit (28) receives a regulated voltage and provides a reference voltage having a low voltage level and a high voltage level. The low voltage level and the high voltage level control the logic high voltage of an output data signal. During a transition from a logic low voltage to a logic high voltage of the output data signal, the output data signal is allowed to overshoot the low voltage level. After the transition is complete, the output data signal settles at the high voltage level. This limits the amount of overshoot of the output data signal. The clamping circuit (40) dampens the oscillations of the output signal.

Abstract: A cache TAG comparator (20) has a combined data multiplexer and compare circuit (30) for multiplexing redundant columns (26) with normal columns of memory cells and for comparing input data with a TAG address stored in a TAG array (21) for determining if data required by a data processing system is located in a corresponding cache memory. A BICMOS match logic circuit (40) receives a compare signal from each data multiplexer and compare circuit, and provides a logic high match signal indicating a cache hit in response to a logic state of the input data and the TAG address being identical. The comparison is performed in ECL, allowing high speed operation. Also, the match signal is generated prior to a critical read path, insuring faster generation of the match signal.

Abstract: A driver circuit (33) for output buffers or the like provides differing switching speed and di/dt depending on whether an output signal is switched in response to input signals or a control signal.

Abstract: A memory (20) has N.sub.BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V.sub.CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V.sub.AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V.sub.AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.

Abstract: A memory (50) having a BICMOS sense amplifier (20) includes a differential amplifier stage (11), emitter-follower input transistors (25 and 26), and emitter-follower output transistors (27 and 28). When sense amplifier (20) is deselected, P-channel transistors (31-37) pull the bases of the bipolar transistors (23-28) to V.sub.DD -2V.sub.BE and P-channel transistors (29 and 30) decouple the bases of emitter-follower output transistors (27 and 28) from the collectors of transistors (23 and 24). At the same time, N-channel transistors (38, 40, 42, 44, and 46) decouple N-channel transistors (39, 41, 43, 45, and 47) from the emitters of bipolar transistors (23-28). Thus, no current can flow, reducing the power consumption of sense amplifier (20). Also, bipolar transistors (23-28) are prevented from being excessively reverse-biased. Additionally, a plurality of sense amplifiers (20) can have their outputs wired-OR connected.

Abstract: A regulated BiCMOS output buffer (34) regulates a logic high voltage of an output signal to improve interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.

Abstract: A parity SRAM having the capability to support byte parity is provided. The parity SRAM uses four (4) independent byte write enable (BWE.sub.x) signals to enable a write amplifier to individually write a single parity bit to a selected memory location. The SRAM is designed to function in either a parity or a non-parity mode. A bonding option pad is connected to parity control logic circuitry, and determines whether the SRAM will function in the parity mode or the non-parity mode. The parity control logic circuitry generates a parity signal, based on the electrical connection of the option pad. Thus, when the option pad is connected to ground, the parity option is selected, whereas, when the option pad is connected to a positive power supply, then non-parity functionality is selected. When parity functionality is selected, the the SRAM will allow the four (4) independent BWE.sub.x signals to individually enable the write amplifier.

Abstract: An output buffer in an integrated circuit comprising voltage regulator, a predriver, and an output stage. The integrated circuit comprises a chip and a package and interconnections therebetween. The voltage regulator is coupled to a first power supply voltage terminal and a second power supply voltage terminal, and provides a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations in voltage between the first power supply voltage terminal and the second power supply voltage terminal. The predriver receives the regulated voltage signal and a data input signal and provides a regulated predriven signal in response to the data signal. The output stage receives the regulated predriven signal and provides an output signal in response thereto. The output signal is driven onto a bonding pad of the device to provide an interconnection point between the chip and the package.