Patents by Inventor Taishi ISHIKURA
Taishi ISHIKURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10199391Abstract: A semiconductor device includes an under layer, a stacked body comprising a plurality of conductive layers and insulating layers alternately stacked one over the other in a stacking direction, above the insulating layer, a columnar portion extending into the stacked body in the stacking direction of the stacked body, and a graphene film between at least one of the conductive layers and adjacent insulating layers and between the at least one of the conductive layers and the columnar portion.Type: GrantFiled: August 28, 2017Date of Patent: February 5, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Taishi Ishikura, Atsunobu Isobayashi, Masayuki Kitamura, Akihiro Kajita
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Publication number: 20180261624Abstract: A semiconductor device includes an under layer, a stacked body comprising a plurality of conductive layers and insulating layers alternately stacked one over the other in a stacking direction, above the insulating layer, a columnar portion extending into the stacked body in the stacking direction of the stacked body, and a graphene film between at least one of the conductive layers and adjacent insulating layers and between the at least one of the conductive layers and the columnar portion.Type: ApplicationFiled: August 28, 2017Publication date: September 13, 2018Inventors: Taishi ISHIKURA, Atsunobu ISOBAYASHI, Masayuki KITAMURA, Akihiro KAJITA
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Patent number: 9924593Abstract: A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.Type: GrantFiled: September 1, 2016Date of Patent: March 20, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Sakai, Yuichi Yamazaki, Hisao Miyazaki, Masayuki Katagiri, Taishi Ishikura, Akihiro Kajita
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Patent number: 9880464Abstract: According to one embodiment, an imprint pattern forming method includes providing a substrate with a pattern formation region and a peripheral region, the peripheral region having a surface lower than a surface of the pattern formation region, located at a periphery of the pattern formation region. The method includes forming an auxiliary pattern with a predetermined height on at least a portion of the peripheral region, providing a resist layer on at least the pattern formation region, and imprinting the resist layer using a template by locating the template in a region which includes a portion of the pattern formation region and a portion of the peripheral region.Type: GrantFiled: August 26, 2016Date of Patent: January 30, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Daisuke Kawamura, Koji Matsuo, Masanobu Baba, Tatsuro Shinozaki, Taishi Ishikura
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Patent number: 9741663Abstract: According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.Type: GrantFiled: March 10, 2016Date of Patent: August 22, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Taishi Ishikura, Atsunobu Isobayashi, Tatsuro Saito, Akihiro Kajita, Tadashi Sakai
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Publication number: 20170184958Abstract: According to one embodiment, an imprint pattern forming method includes providing a substrate with a pattern formation region and a peripheral region, the peripheral region having a surface lower than a surface of the pattern formation region, located at a periphery of the pattern formation region. The method includes forming an auxiliary pattern with a predetermined height on at least a portion of the peripheral region, providing a resist layer on at least the pattern formation region, and imprinting the resist layer using a template by locating the template in a region which includes a portion of the pattern formation region and a portion of the peripheral region.Type: ApplicationFiled: August 26, 2016Publication date: June 29, 2017Inventors: Daisuke KAWAMURA, Koji MATSUO, Masanobu BABA, Tatsuro SHINOZAKI, Taishi ISHIKURA
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Publication number: 20170079138Abstract: A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.Type: ApplicationFiled: September 1, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tadashi SAKAI, Yuichi YAMAZAKI, Hisao MIYAZAKI, Masayuki KATAGIRI, Taishi ISHIKURA, Akihiro KAJITA
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Publication number: 20170069576Abstract: According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.Type: ApplicationFiled: March 10, 2016Publication date: March 9, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taishi ISHIKURA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Akihiro KAJITA, Tadashi SAKAI
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Patent number: 9576905Abstract: A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer, a third wiring comprising a second conductive material different from the first conductive material, and an insulation film on the semiconductor layer between the first wiring and the second wiring and between the second wiring and the third wiring. The second wiring is provided on at least two sides of the third wiring, and a mean free path of free electrons in the first conductive material is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material shows quantized conduction and the second conductive material does not show quantized conduction. The first wiring, the second wiring, the third wiring, and the insulation film are in one wiring layer provided on the semiconductor layer.Type: GrantFiled: February 24, 2016Date of Patent: February 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Taishi Ishikura, Atsunobu Isobayashi, Akihiro Kajita
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Patent number: 9484206Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.Type: GrantFiled: March 3, 2015Date of Patent: November 1, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Taishi Ishikura, Akihiro Kajita, Tadashi Sakai, Atsunobu Isobayashi, Makoto Wada, Tatsuro Saito, Masayuki Kitamura, Atsuko Sakata
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Publication number: 20160276219Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a graphene film on a catalytic layer, removing a part of the graphene film to form an exposed side surface of the graphene film, introducing dopant into the graphene film from the exposed side surface, and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.Type: ApplicationFiled: August 31, 2015Publication date: September 22, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto WADA, Yuichi YAMAZAKI, Hisao MIYAZAKI, Akihiro KAJITA, Tatsuro SAITO, Atsunobu ISOBAYASHI, Taishi ISHIKURA, Masayuki KATAGIRI, Tadashi SAKAI
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Publication number: 20160268200Abstract: A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer, a third wiring comprising a second conductive material different from the first conductive material, and an insulation film on the semiconductor layer between the first wiring and the second wiring and between the second wiring and the third wiring. The second wiring is provided on at least two sides of the third wiring, and a mean free path of free electrons in the first conductive material is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material shows quantized conduction and the second conductive material does not show quantized conduction. The first wiring, the second wiring, the third wiring, and the insulation film are in one wiring layer provided on the semiconductor layer.Type: ApplicationFiled: February 24, 2016Publication date: September 15, 2016Inventors: Taishi ISHIKURA, Atsunobu ISOBAYASHI, Akihiro KAJITA
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Publication number: 20160079176Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a first film having a first melting point, forming a pattern of a second film on an upper surface of the first film, the second film having a second melting point lower than the first melting point, and forming a graphene film on the upper surface of the first film, the graphene film being formed from a side surface of the pattern of the second film.Type: ApplicationFiled: March 12, 2015Publication date: March 17, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsunobu ISOBAYASHI, Masayuki KITAMURA, Yuichi YAMAZAKI, Akihiro KAJITA, Tatsuro SAITO, Taishi ISHIKURA, Atsuko SAKATA, Tadashi SAKAI, Makoto WADA
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Publication number: 20160056256Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.Type: ApplicationFiled: March 3, 2015Publication date: February 25, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taishi ISHIKURA, Akihiro KAJITA, Tadashi SAKAI, Atsunobu ISOBAYASHI, Makoto WADA, Tatsuro SAITO, Masayuki KITAMURA, Atsuko SAKATA
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Patent number: 9236268Abstract: In the manufacturing method of a semiconductor device according to the present embodiment, a resist is supplied on a base material. A template including a first template region having a device pattern and a second template region being adjacent to the device pattern and having supporting column patterns is pressed against the resist on the base material. The resist is cured, thereby transferring the device pattern to the resist on a first material region of the base material corresponding to the first template region and at the same time transferring the supporting column patterns to the resist on a second material region of the base material corresponding to the second template region to form supporting columns. The supporting columns are contacted with the first template region when the device pattern is transferred to a resist supplied to the second material region.Type: GrantFiled: February 4, 2014Date of Patent: January 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Taishi Ishikura, Atsunobu Isobayashi, Akihiro Kajita
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Publication number: 20150228538Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, an interlayer insulation film, a plug, a first mark, a second mark, and an upper wiring. The substrate has a device region and a mark formation region. The interlayer insulation film is formed on the substrate. The plug is made of a first metal material in the interlayer insulation film on the device region of the substrate. The first mark is made of the first metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark is made of a second metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark has a concave on a surface thereof. The upper wiring is formed on the interlayer insulation film and is electrically connected to the plug.Type: ApplicationFiled: July 28, 2014Publication date: August 13, 2015Inventors: Makoto WADA, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Taishi ISHIKURA
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Patent number: 9030012Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.Type: GrantFiled: January 14, 2014Date of Patent: May 12, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Wada, Akihiro Kajita, Atsunobu Isobayashi, Tatsuro Saito, Tadashi Sakai, Taishi Ishikura
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Publication number: 20150111393Abstract: In the manufacturing method of a semiconductor device according to the present embodiment, a resist is supplied on a base material. A template including a first template region having a device pattern and a second template region being adjacent to the device pattern and having supporting column patterns is pressed against the resist on the base material. The resist is cured, thereby transferring the device pattern to the resist on a first material region of the base material corresponding to the first template region and at the same time transferring the supporting column patterns to the resist on a second material region of the base material corresponding to the second template region to form supporting columns. The supporting columns are contacted with the first template region when the device pattern is transferred to a resist supplied to the second material region.Type: ApplicationFiled: February 4, 2014Publication date: April 23, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taishi ISHIKURA, Atsunobu ISOBAYASHI, Akihiro KAJITA
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Publication number: 20150035149Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.Type: ApplicationFiled: January 14, 2014Publication date: February 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto WADA, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Tadashi SAKAI, Taishi ISHIKURA