Patents by Inventor Taishi Kubota
Taishi Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7592234Abstract: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.Type: GrantFiled: August 3, 2007Date of Patent: September 22, 2009Assignee: Elpida Memory, Inc.Inventors: Takuo Ohashi, Taishi Kubota
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Publication number: 20080032509Abstract: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.Type: ApplicationFiled: August 3, 2007Publication date: February 7, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Takuo OHASHI, Taishi KUBOTA
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Publication number: 20070099364Abstract: A method for forming a semiconductor device having a polymetal gate electrode includes the steps of forming a gate oxide film on a silicon substrate, forming a polysilicon film and a tungsten film on the gate oxide film, patterning the polysilicon film and tungsten film, and thermally oxidizing the polysilicon film in an oxidizing atmosphere including water and hydrogen at a substrate-surface temperature of 850 degrees C. and a water content of 7% to 20%.Type: ApplicationFiled: October 26, 2006Publication date: May 3, 2007Inventors: Takuo Ohashi, Taishi Kubota, Toru Miyazaki, Shigetomi Michimata, Satoru Yamada
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Patent number: 7163871Abstract: A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.Type: GrantFiled: January 26, 2004Date of Patent: January 16, 2007Assignee: Elpida Memory, Inc.Inventors: Taishi Kubota, Yoshihiro Kitamura, Takuo Ohashi, Susumu Sakurai, Takayuki Kanda, Shinichi Horibe
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Publication number: 20060166459Abstract: In a method of producing a semiconductor apparatus, which method includes a trench forming step of forming a trench in a silicon substrate and an inner wall oxidizing step of forming an oxide film on an inner wall of the trench; the inner wall oxidizing step being performed by wet oxidization with a low concentration of moisture mixed in oxygen to form the oxide film so that a stress caused between the oxide film and the silicon substrate is not greater than 3.5×109 (dyne/cm2) and a radius at a corner of the trench is 8 nm or more.Type: ApplicationFiled: January 25, 2006Publication date: July 27, 2006Applicant: ELPIDA MEMORY, INC.Inventors: Takuo Ohashi, Takeshi Suwa, Susumu Sakurai, Taishi Kubota
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Publication number: 20050227452Abstract: A method for producing a semiconductor device includes the steps of forming a trench for device isolation on a silicon substrate; and annealing the silicon substrate in an atmosphere containing a noble gas at any step after the growth of a buried oxide film until the growth of a gate polysilicon.Type: ApplicationFiled: April 12, 2005Publication date: October 13, 2005Inventors: Takuo Ohashi, Takeshi Suwa, Taishi Kubota
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Publication number: 20050215026Abstract: With respect to nitriding of an oxide film on an inner wall of a trench, a method for producing a semiconductor device is provided, the method preventing the characteristic deterioration of the semiconductor device by controlling and optimizing peak nitrogen concentration in an oxide film to reduce the stress and to suppress the threshold voltage shift due to the positive charge of nitrogen.Type: ApplicationFiled: March 24, 2005Publication date: September 29, 2005Applicant: Elpida Memory, Inc.Inventors: Takuo Ohashi, Taishi Kubota, Susumu Sakurai, Takayuki Kanda
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Publication number: 20040214404Abstract: A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.Type: ApplicationFiled: January 26, 2004Publication date: October 28, 2004Inventors: Taishi Kubota, Yoshihiro Kitamura, Takuo Ohashi, Susumu Sakurai, Takayuki Kanda, Shinichi Horibe
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Patent number: 6300185Abstract: In a method of forming a polycrystalline silicon film, the polycrystalline silicon film is formed under film formation conditions of a film formation rate of 0.9rav to 1.1rav, where rav (nm/minute) is an average rate of forming the polycrystalline silicon film on each of a plurality of substrates on which oxide films are formed so as to provide the roughness of the interface between the oxide film on the substrate and the polycrystalline silicon film of less than 1 nm. As a result, it is possible to decrease the roughness of the interface between a gate oxide film and the polycrystalline silicon film and to improve reliability for ensuring the long-time use of the gate oxide film.Type: GrantFiled: July 1, 1999Date of Patent: October 9, 2001Assignee: NEC CorporationInventor: Taishi Kubota
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Patent number: 5972750Abstract: There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.Type: GrantFiled: February 2, 1998Date of Patent: October 26, 1999Assignee: NEC CorporationInventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa
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Patent number: 5973355Abstract: There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.Type: GrantFiled: May 5, 1997Date of Patent: October 26, 1999Assignee: NEC CorporationInventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa
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Patent number: 5757044Abstract: A floating gate type field effect transistor has a plurality of floating gate sub-electrodes on a lower gate oxide layer electrically isolated from one another; even if one of the floating gate sub-electrodes changes a part of a channel region thereunder to depletion state due to an over-erase, the over-erase does not affect the function of the floating gate type field effect transistor, because another sub-electrode transfers and cuts off channel current depending upon the amount of electrons accumulated therein.Type: GrantFiled: October 26, 1995Date of Patent: May 26, 1998Assignee: NEC CorporationInventor: Taishi Kubota
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Patent number: 5065215Abstract: A semiconductor memory includes a plurality of semiconductor memory cells formed in a matrix form on a semiconductor substrate, each semiconductor memory cell having a memory cell including a trench capacitor, a bit line, and a word line extending perpendicularly to the bit line. The word lines of semiconductor memory cells adjacent in a direction of the bit lines substantially vertically overlap each other. A method of manufacturing the above semiconductor memory includes the steps of forming a first word line of a given semiconductor memory cell, and forming a second word line of a semiconductor memory cell adjacent to the given semiconductor memory cell in a direction of the bit line on the first word line, so that the second word line overlaps the first word line in a substantially insulated state.Type: GrantFiled: June 22, 1990Date of Patent: November 12, 1991Assignee: NEC CorporationInventor: Taishi Kubota
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Patent number: 4868137Abstract: A method of manufacturing an insulated-gate field effect transistor is comprised of forming on a semiconductor substrate a gate electrode elecrically insulated from the substrate. A flat insulating film of silicon oxide is formed over the substrate. A pair of openings are formed through the flat insulating film at both sides of the gate electrode such that opposite side thereof are etched and exposed. An oxide film is formed on the exposed side edges of the gate electrode. Impurities are implanted through the pair of openings into the substrate to form source and drain regions. An electroconductive polysilicon film is deposited over the substrate. The deposited polysilicon film is polished to leave a part thereof selectively in the openings to thereby form electrical contacts to the source and drain regions through the openings.Type: GrantFiled: December 29, 1988Date of Patent: September 19, 1989Assignee: NEC CorporationInventor: Taishi Kubota