Patents by Inventor Taishi Kubota

Taishi Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7592234
    Abstract: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: September 22, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Takuo Ohashi, Taishi Kubota
  • Publication number: 20080032509
    Abstract: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 7, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Takuo OHASHI, Taishi KUBOTA
  • Publication number: 20070099364
    Abstract: A method for forming a semiconductor device having a polymetal gate electrode includes the steps of forming a gate oxide film on a silicon substrate, forming a polysilicon film and a tungsten film on the gate oxide film, patterning the polysilicon film and tungsten film, and thermally oxidizing the polysilicon film in an oxidizing atmosphere including water and hydrogen at a substrate-surface temperature of 850 degrees C. and a water content of 7% to 20%.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 3, 2007
    Inventors: Takuo Ohashi, Taishi Kubota, Toru Miyazaki, Shigetomi Michimata, Satoru Yamada
  • Patent number: 7163871
    Abstract: A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: January 16, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Taishi Kubota, Yoshihiro Kitamura, Takuo Ohashi, Susumu Sakurai, Takayuki Kanda, Shinichi Horibe
  • Publication number: 20060166459
    Abstract: In a method of producing a semiconductor apparatus, which method includes a trench forming step of forming a trench in a silicon substrate and an inner wall oxidizing step of forming an oxide film on an inner wall of the trench; the inner wall oxidizing step being performed by wet oxidization with a low concentration of moisture mixed in oxygen to form the oxide film so that a stress caused between the oxide film and the silicon substrate is not greater than 3.5×109 (dyne/cm2) and a radius at a corner of the trench is 8 nm or more.
    Type: Application
    Filed: January 25, 2006
    Publication date: July 27, 2006
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Takuo Ohashi, Takeshi Suwa, Susumu Sakurai, Taishi Kubota
  • Publication number: 20050227452
    Abstract: A method for producing a semiconductor device includes the steps of forming a trench for device isolation on a silicon substrate; and annealing the silicon substrate in an atmosphere containing a noble gas at any step after the growth of a buried oxide film until the growth of a gate polysilicon.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 13, 2005
    Inventors: Takuo Ohashi, Takeshi Suwa, Taishi Kubota
  • Publication number: 20050215026
    Abstract: With respect to nitriding of an oxide film on an inner wall of a trench, a method for producing a semiconductor device is provided, the method preventing the characteristic deterioration of the semiconductor device by controlling and optimizing peak nitrogen concentration in an oxide film to reduce the stress and to suppress the threshold voltage shift due to the positive charge of nitrogen.
    Type: Application
    Filed: March 24, 2005
    Publication date: September 29, 2005
    Applicant: Elpida Memory, Inc.
    Inventors: Takuo Ohashi, Taishi Kubota, Susumu Sakurai, Takayuki Kanda
  • Publication number: 20040214404
    Abstract: A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.
    Type: Application
    Filed: January 26, 2004
    Publication date: October 28, 2004
    Inventors: Taishi Kubota, Yoshihiro Kitamura, Takuo Ohashi, Susumu Sakurai, Takayuki Kanda, Shinichi Horibe
  • Patent number: 6300185
    Abstract: In a method of forming a polycrystalline silicon film, the polycrystalline silicon film is formed under film formation conditions of a film formation rate of 0.9rav to 1.1rav, where rav (nm/minute) is an average rate of forming the polycrystalline silicon film on each of a plurality of substrates on which oxide films are formed so as to provide the roughness of the interface between the oxide film on the substrate and the polycrystalline silicon film of less than 1 nm. As a result, it is possible to decrease the roughness of the interface between a gate oxide film and the polycrystalline silicon film and to improve reliability for ensuring the long-time use of the gate oxide film.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: October 9, 2001
    Assignee: NEC Corporation
    Inventor: Taishi Kubota
  • Patent number: 5972750
    Abstract: There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa
  • Patent number: 5973355
    Abstract: There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa
  • Patent number: 5757044
    Abstract: A floating gate type field effect transistor has a plurality of floating gate sub-electrodes on a lower gate oxide layer electrically isolated from one another; even if one of the floating gate sub-electrodes changes a part of a channel region thereunder to depletion state due to an over-erase, the over-erase does not affect the function of the floating gate type field effect transistor, because another sub-electrode transfers and cuts off channel current depending upon the amount of electrons accumulated therein.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: May 26, 1998
    Assignee: NEC Corporation
    Inventor: Taishi Kubota
  • Patent number: 5065215
    Abstract: A semiconductor memory includes a plurality of semiconductor memory cells formed in a matrix form on a semiconductor substrate, each semiconductor memory cell having a memory cell including a trench capacitor, a bit line, and a word line extending perpendicularly to the bit line. The word lines of semiconductor memory cells adjacent in a direction of the bit lines substantially vertically overlap each other. A method of manufacturing the above semiconductor memory includes the steps of forming a first word line of a given semiconductor memory cell, and forming a second word line of a semiconductor memory cell adjacent to the given semiconductor memory cell in a direction of the bit line on the first word line, so that the second word line overlaps the first word line in a substantially insulated state.
    Type: Grant
    Filed: June 22, 1990
    Date of Patent: November 12, 1991
    Assignee: NEC Corporation
    Inventor: Taishi Kubota
  • Patent number: 4868137
    Abstract: A method of manufacturing an insulated-gate field effect transistor is comprised of forming on a semiconductor substrate a gate electrode elecrically insulated from the substrate. A flat insulating film of silicon oxide is formed over the substrate. A pair of openings are formed through the flat insulating film at both sides of the gate electrode such that opposite side thereof are etched and exposed. An oxide film is formed on the exposed side edges of the gate electrode. Impurities are implanted through the pair of openings into the substrate to form source and drain regions. An electroconductive polysilicon film is deposited over the substrate. The deposited polysilicon film is polished to leave a part thereof selectively in the openings to thereby form electrical contacts to the source and drain regions through the openings.
    Type: Grant
    Filed: December 29, 1988
    Date of Patent: September 19, 1989
    Assignee: NEC Corporation
    Inventor: Taishi Kubota