Patents by Inventor Taishi WAKABAYASHI
Taishi WAKABAYASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230154748Abstract: A method for manufacturing a semiconductor substrate by forming an insulator film and a semiconductor single crystal layer on a surface of a silicon single crystal substrate to manufacture a semiconductor substrate having the semiconductor single crystal layer on the insulator film, the method including at least the steps of: forming a silicon nitride film having an epitaxial relationship with the silicon single crystal substrate on the surface of the silicon single crystal substrate as the insulator film by subjecting the silicon single crystal substrate to a heat treatment under a nitrogen gas-containing atmosphere; and forming the semiconductor single crystal layer on the silicon nitride film by epitaxial growth. This makes it possible to obtain a semiconductor substrate by simple method with high productivity at low cost even when the insulator film provided between the silicon single crystal substrate and the semiconductor single crystal layer is a silicon nitride film.Type: ApplicationFiled: October 8, 2020Publication date: May 18, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Miho NIITANI, Taishi WAKABAYASHI, Kento YAMADA, Kazuhiko YOSHIDA
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Patent number: 11495488Abstract: A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 ?·cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.Type: GrantFiled: May 14, 2019Date of Patent: November 8, 2022Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Toshikazu Imai, Kazuhiko Yoshida, Miho Niitani, Taishi Wakabayashi, Osamu Ishikawa
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Publication number: 20210249301Abstract: A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 ?·cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.Type: ApplicationFiled: May 14, 2019Publication date: August 12, 2021Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Toshikazu IMAI, Kazuhiko YOSHIDA, Miho NIITANI, Taishi WAKABAYASHI, Osamu ISHIKAWA
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Patent number: 10763127Abstract: A heat treatment method for a semiconductor wafer includes: heat treatment in a heat treatment furnace of single wafer processing type having a susceptor capable of mounting a semiconductor wafer, the heat treatment being performed on a semiconductor wafer mounted on the susceptor disposed in the heat treatment furnace; and pre-heating to hold the temperature in the heat treatment furnace at a prescribed temperature lower than the temperature of the heat treatment for a prescribed period before the heat treatment, holding the semiconductor wafer separated from the susceptor during the pre-heating. This heat treatment method for a semiconductor wafer makes it possible to reduce the slip of a semiconductor wafer without largely lowering the productivity even in a high-temperature heat treatment.Type: GrantFiled: January 26, 2017Date of Patent: September 1, 2020Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Taishi Wakabayashi, Miho Niitani, Kenji Meguro
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Patent number: 10566196Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.Type: GrantFiled: March 14, 2016Date of Patent: February 18, 2020Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro Kobayashi, Osamu Ishikawa, Kenji Meguro, Taishi Wakabayashi, Hiroyuki Oonishi
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Patent number: 10529615Abstract: A bonded SOI wafer is manufactured by bonding a bond and a base wafer, each composed of a silicon single crystal, via an insulator film, depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; wherein, the base wafer is a silicon single crystal wafer having a resistivity of 100 ?·cm or more, depositing the polycrystalline silicon layer further includes a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited, and the polycrystalline silicon layer is deposited at a temperature of 900° C. or more.Type: GrantFiled: March 5, 2015Date of Patent: January 7, 2020Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Kenji Meguro, Taishi Wakabayashi, Norihiro Kobayashi
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Patent number: 10460983Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.Type: GrantFiled: March 4, 2015Date of Patent: October 29, 2019Assignee: SHIN-ETSU HANDOTAI CO.,LTD.Inventors: Taishi Wakabayashi, Kenji Meguro, Masatake Nakano, Shinichiro Yagi, Tomosuke Yoshida
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Publication number: 20190035639Abstract: A heat treatment method for a semiconductor wafer includes: heat treatment in a heat treatment furnace of single wafer processing type having a susceptor capable of mounting a semiconductor wafer, the heat treatment being performed on a semiconductor wafer mounted on the susceptor disposed in the heat treatment furnace; and pre-heating to hold the temperature in the heat treatment furnace at a prescribed temperature lower than the temperature of the heat treatment for a prescribed period before the heat treatment, holding the semiconductor wafer separated from the susceptor during the pre-heating. This heat treatment method for a semiconductor wafer makes it possible to reduce the slip of a semiconductor wafer without largely lowering the productivity even in a high-temperature heat treatment.Type: ApplicationFiled: January 26, 2017Publication date: January 31, 2019Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Taishi WAKABAYASHI, Miho NIITANI, Kenji MEGURO
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Publication number: 20180122639Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?-cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.Type: ApplicationFiled: March 14, 2016Publication date: May 3, 2018Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro KOBAYASHI, Osamu ISHIKAWA, Kenji MEGURO, Taishi WAKABAYASHI, Hiroyuki OONISHI
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Publication number: 20170040210Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.Type: ApplicationFiled: March 4, 2015Publication date: February 9, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Taishi WAKABAYASHI, Kenji MEGURO, Masatake NAKANO, Shinichiro YAGI, Tomosuke YOSHIDA
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Publication number: 20170033002Abstract: A bonded SOI wafer is manufactured by bonding a bond and a base wafer, each composed of a silicon single crystal, via an insulator film, depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; wherein, the base wafer is a silicon single crystal wafer having a resistivity of 100 ?·cm or more, depositing the polycrystalline silicon layer further includes a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited, and the polycrystalline silicon layer is deposited at a temperature of 900° C. or more.Type: ApplicationFiled: March 5, 2015Publication date: February 2, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Kenji MEGURO, Taishi WAKABAYASHI, Norihiro KOBAYASHI