Patents by Inventor Taisuke Shiroyama

Taisuke Shiroyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for producing multilayer wiring boards
    Patent number: 6228465
    Abstract: An improved process for producing a multilayer wiring board that has a plurality of conductor patterns and an interlevel dielectric layer on at least one surface of a substrate, with via holes or trench-like channels being provided at specified sites of said interlevel dielectric layer to establish an electrical interconnection between said conductor patterns, wherein prior to the provision of said via holes or trench-like channels, a coating having resistance to sandblasting is formed in a pattern over the interlevel dielectric layer and then sandblasting is performed to remove the interlevel dielectric layer in selected areas to form the via holes or trench-like channels and, thereafter, the coating having resistance to sandblasting is removed, followed by the provision of a conductive layer.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: May 8, 2001
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Yoshikazu Takiguchi, Hiroyuki Obiya, Toru Takahashi, Taisuke Shiroyama, Kenji Tazawa
  • Process for producing multilayer wiring boards
    Patent number: 6010956
    Abstract: An improved process for producing a multilayer wiring board that has a plurality of conductor patterns and an interlevel dielectric layer on at least one surface of a substrate, with via holes or trench-like channels being provided at specified sites of said interlevel dielectric layer to establish an electrical interconnection between said conductor patterns, wherein prior to the provision of said via holes or trench-like channels, a coating having resistance to sandblasting is formed in a pattern over the interlevel dielectric layer and then sandblasting is performed to remove the interlevel dielectric layer in selected areas to form the via holes or trench-like channels and, thereafter, the coating having resistance to sandblasting is removed, followed by the provision of a conductive layer.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: January 4, 2000
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Yoshikazu Takiguchi, Hiroyuki Obiya, Toru Takahashi, Taisuke Shiroyama, Kenji Tazawa