Patents by Inventor Tai Uk Rim

Tai Uk Rim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121945
    Abstract: A semiconductor memory device comprises a substrate including a first source/drain region and a second source/drain region, a trench between the first source/drain region and the second source/drain region and formed in the substrate, a cell gate insulating layer on sidewalls and a bottom surface of the trench, a cell gate electrode on the cell gate insulating layer, a work function control pattern on the cell gate electrode, including N-type impurities and a cell gate capping pattern on the work function control pattern. The work function control pattern includes a semiconductor material. The work function control pattern includes a first region and a second region between the first region and the cell gate electrode. A concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region.
    Type: Application
    Filed: July 6, 2023
    Publication date: April 11, 2024
    Inventors: Jin-Seong Lee, Tai Uk Rim, Ji Hun Kim, Kyo-Suk Chae
  • Publication number: 20200203351
    Abstract: A memory device includes: a substrate including a first active region and a second active region spaced apart from each other; a device isolation film on the substrate, the device isolation film defining the first active region and the second active region; and a buried word line structure passing a low dielectric region between the first active region and the second active region, wherein the buried word line structure includes a gate electrode in a gate trench and a gate insulating layer between a portion of the gate electrode outside the low dielectric region and the gate trench, and wherein an air gap is disposed between a portion of the gate electrode within the low dielectric region and the gate trench.
    Type: Application
    Filed: September 7, 2019
    Publication date: June 25, 2020
    Inventors: Kyo-suk CHAE, Tai-uk RIM, Hyeon-kyun NOH, Won-sok LEE
  • Patent number: 9559230
    Abstract: Disclosed are a solar cell and a method for manufacturing the same. The solar cell comprises asymmetric nanowires each of which has an angled sidewall, and thus incident light can be concentrated at a p-n junction portion by means of a total reflection phenomenon of light caused by the difference between the refractive indices of a semiconductor layer and a transparent electrode layer, and light absorption may increase due to an increase in the light travel distance, thus improving photoelectric efficiency. Further, the method for manufacturing the solar cell involves etching a substrate and integrally forming the substrate and a p-type semiconductor layer including the asymmetric nanowires each of which has the angled sidewalls, thereby enabling reduced manufacturing costs and simple and easy manufacture of the nanowires having the angled sidewalls.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: January 31, 2017
    Assignee: POSTECH ACADEMY—INDUSTRY FOUNDATION
    Inventors: Chang Ki Baek, Yoon Ha Jeong, Seong Wook Choi, Tai Uk Rim, Soo Young Park, Myung Dong Ko
  • Patent number: 9461157
    Abstract: The present invention provides a nanowire sensor comprising nanowires, in which the nanowires are stacked to form a three-dimensional structure so that they have a large exposed surface area compared to that of a conventional straight nanowire sensor in the same limited area, thereby increasing the probability of attachment of a target material to the nanowires to thereby increase the measurement sensitivity of the sensor. Thus, a change in the electrical conductivity (conductance or resistance) of the nanowires can be sensed with higher sensitivity, suggesting that the sensor has increased sensitivity.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: October 4, 2016
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jeong Soo Lee, Yoon Ha Jeong, Sung Ho Kim, Ki Hyun Kim, Tai Uk Rim, Chang Ki Baek
  • Publication number: 20150303289
    Abstract: The present invention provides a nanowire sensor comprising nanowires, in which the nanowires are stacked to form a three-dimensional structure so that they have a large exposed surface area compared to that of a conventional straight nanowire sensor in the same limited area, thereby increasing the probability of attachment of a target material to the nanowires to thereby increase the measurement sensitivity of the sensor. Thus, a change in the electrical conductivity (conductance or resistance) of the nanowires can be sensed with higher sensitivity, suggesting that the sensor has increased sensitivity.
    Type: Application
    Filed: November 22, 2013
    Publication date: October 22, 2015
    Inventors: Jeong Soo LEE, Yoon Ha JEONG, Sung Ho KIM, Ki Hyun KIM, Tai Uk RIM, Chang Ki BAEK
  • Patent number: 9099543
    Abstract: A nanowire sensor having a nanowire in a network structure includes: source and drain electrodes formed over a substrate; a nanowire formed between the source and drain electrodes and having a network structure in which patterns of intersections are repeated; and a detection material fixed to the nanowire and selectively reacting with a target material introduced from outside.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 4, 2015
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jeong Soo Lee, Yoon Ha Jeong, Tai Uk Rim, Chang Ki Baek, Sung Ho Kim, Ki Hyun Kim
  • Publication number: 20140326305
    Abstract: Disclosed are a solar cell and a method for manufacturing the same. The solar cell comprises asymmetric nanowires each of which has an angled sidewall, and thus incident light can be concentrated at a p-n junction portion by means of a total reflection phenomenon of light caused by the difference between the refractive indices of a semiconductor layer and a transparent electrode layer, and light absorption may increase due to an increase in the light travel distance, thus improving photoelectric efficiency. Further, the method for manufacturing the solar cell involves etching a substrate and integrally forming the substrate and a p-type semiconductor layer including the asymmetric nanowires each of which has the angled sidewalls, thereby enabling reduced manufacturing costs and simple and easy manufacture of the nanowires having the angled sidewalls.
    Type: Application
    Filed: August 17, 2012
    Publication date: November 6, 2014
    Inventors: Chang Ki Baek, Yoon Ha Jeong, Seong Wook Choi, Tai Uk Rim, Soo Young Park, Myung Dong Ko
  • Publication number: 20140034907
    Abstract: A nanowire sensor having a nanowire in a network structure includes: source and drain electrodes formed over a substrate; a nanowire formed between the source and drain electrodes and having a network structure in which patterns of intersections are repeated; and a detection material fixed to the nanowire and selectively reacting with a target material introduced from outside.
    Type: Application
    Filed: March 19, 2012
    Publication date: February 6, 2014
    Inventors: Jeong Soo Lee, Yoon Ha Jeong, Tai Uk Rim, Chang Ki Baek, Sung Ho Kim, Ki Hyun Kim