Patents by Inventor TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR REMOVING A PATTERNED HARD MASK LAYER
    Publication number: 20140120729
    Abstract: The present disclosure provides embodiments of a method that includes providing a substrate having a patterned material layer and a patterned hard mask layer disposed on the patterned material layer, wherein the patterned material layer includes a material feature having a first dimension and the patterned hard mask layer includes a hard mask feature covering the material feature. The method also includes forming, on the substrate and the hard mask feature, a patterned resist layer with an opening that exposes the hard mask feature and has a second dimension as a function of the first dimension; etching back the resist film; and removing the patterned hard mask layer.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • MEMORY ARCHITECTURE
    Publication number: 20140119135
    Abstract: A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value flowing through the transistor is determined when the transistor is in on. A first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on. Based on the first current value, the second current value, and a relationship between the first current value and the second current value, a number of memory cells to be coupled with a data line associated with the memory cell is determined.
    Type: Application
    Filed: March 11, 2013
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Interconnection Structure
    Publication number: 20140117534
    Abstract: A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company. Ltd.
  • MEMORY ARCHITECTURE
    Publication number: 20140119138
    Abstract: A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit.
    Type: Application
    Filed: March 8, 2013
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
  • Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices
    Publication number: 20140117533
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • BARRIER LAYER FOR COPPER INTERCONNECT
    Publication number: 20140117547
    Abstract: A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • System and Method for Improving a Lithography Simulation Model
    Publication number: 20140123084
    Abstract: A method of performing initial optical proximity correction (OPC) with a calibrated lithography simulation model. The method includes providing a photomask having an integrated circuit (IC) pattern formed thereon, acquiring an aerial image of the IC pattern formed on the photomask using an optical microscope, and calibrating an optical component of the lithography simulation model based on the aerial image. The method also includes exposing and developing a photoresist layer on a semiconductor wafer using the photomask to form a post-development pattern on the photoresist layer, acquiring a post-development image of the post-development pattern on the photoresist layer, and calibrating the photoresist component of the lithography simulation model based on the post-development image.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Metal-Oxide-Semiconductor Field-Effect Transistor with Spacer over Gate
    Publication number: 20140117467
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Fan-Out Wafer Level Package Structure
    Publication number: 20140110856
    Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Ltd.
  • Metal Bump Joint Structure
    Publication number: 20140110839
    Abstract: A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods
    Publication number: 20140110836
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • MEMS Devices and Fabrication Methods Thereof
    Publication number: 20140103461
    Abstract: A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate.
    Type: Application
    Filed: March 14, 2013
    Publication date: April 17, 2014
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Reticle Transfer System and Method
    Publication number: 20140098354
    Abstract: A fabrication system comprises a global system comprising a plurality of stockers and a global transportation system connected to the stockers, a local system coupled to the global system through the global transportation system, wherein the local system comprises a first buffer located at a boundary between the global system and the local system, a plurality of lithography apparatuses coupled to the first buffer through a local transportation system and an empty pod buffer.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Apparatus and Method for a Component Package
    Publication number: 20140091471
    Abstract: A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Implant Isolated Devices and Method for Forming the Same
    Publication number: 20140091377
    Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • MULTIPLE METAL LAYER SEMICONDUCTOR DEVICE AND LOW TEMPERATURE STACKING METHOD OF FABRICATING THE SAME
    Publication number: 20140091438
    Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Thermal Dissipation Through Seal Rings in 3DIC Structure
    Publication number: 20140084445
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Seed Layer Structure and Method
    Publication number: 20140084470
    Abstract: A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Contact Structure Of Semiconductor Device
    Publication number: 20140084340
    Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Interconnection Structure and Method of Forming Same
    Publication number: 20140077360
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: January 17, 2013
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.