Patents by Inventor TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME
    Publication number: 20140239306
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • METHOD OF FORMING BUMP STRUCTURE
    Publication number: 20140242791
    Abstract: A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • FInFET Structure and Method for Forming the Same
    Publication number: 20140239404
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first fins are separated from each other by a plurality of first isolation regions and two adjacent second fins are separated from each other by a plurality of second isolation regions. The method further comprises applying a first ion implantation process to the first isolation region, wherein dopants with a first polarity type are implanted in the first isolation region, applying a second ion implantation process to the second isolation region, wherein dopants with a second polarity type are implanted in the second isolation region and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • SEMICONDUCTOR DEVICE CONTAINING HEMT AND MISFET AND METHOD OF FORMING THE SAME
    Publication number: 20140239350
    Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • INTEGRATED CIRCUIT INTERCONNECTS AND METHODS OF MAKING SAME
    Publication number: 20140239501
    Abstract: A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • STARTUP CIRCUIT AND METHOD FOR AC-DC CONVERTERS
    Publication number: 20140233283
    Abstract: An AC-DC power converter includes a rectifying unit for generating a rectified voltage, an output stage for converting the rectified voltage into a DC voltage for a load, a controller for controlling the output stage, and a start-up circuit. The start-up circuit includes a start-up voltage generator coupled to the rectifying unit and configured to generate a start-up voltage from the rectified voltage and to output the start-up voltage to the controller to provide power for operation of the controller before the output stage starts outputting power. The start-up voltage generator includes a first depletion mode transistor having a first terminal configured to receive the rectified voltage, a second terminal configured to output at least partially the start-up voltage, and a gate terminal which is grounded.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • MULTI-COMPOSITION DIELECTRIC FOR SEMICONDUCTOR DEVICE
    Publication number: 20140235044
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ILD layer by forming a first portion of an inter-layer dielectric (ILD) layer on a semiconductor substrate; and forming a second portion of an ILD layer on the first portion of the ILD layer. The second portion may have a greater silicon content than the first portion. For example, the second portion may be a silicon rich oxide.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Memory Cell with Decoupled Read/Write Path
    Publication number: 20140233294
    Abstract: A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the gate of the switch and the second line.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Method and Apparatus for Image Sensor Packaging
    Publication number: 20140231887
    Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor in a sensor region and located in a first substrate, wherein the first transistor is electrically coupled to the photodiode. The image sensor further comprises a plurality of logic circuits formed in a second substrate, wherein the second substrate is stacked on the first substrate and the logic circuit are coupled to the first transistor through a plurality of bonding pads, the bonding pads disposed outside of the sensor region.
    Type: Application
    Filed: February 18, 2013
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • High Voltage Transistor Structure and Method
    Publication number: 20140231908
    Abstract: A high voltage transistor structure comprises a first double diffused region and a second double diffused region formed in a first well of a substrate, wherein the first and second double diffused regions are of the same conductivity as the substrate, a first drain/source region formed in the first double diffused region, a first gate electrode formed over the first well and a second drain/source region formed in the second double diffused region. The high voltage transistor structure further comprises a first spacer formed on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer formed on a second side of the first gate electrode and a first oxide protection layer formed between the second drain/source region and the second spacer.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 21, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Molding Compound Structure
    Publication number: 20140231984
    Abstract: A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • BACK SIDE ILLUMINATION (BSI) SENSORS, MANUFACTURING METHODS THEREOF, AND SEMICONDUCTOR DEVICE MANUFACTURING METHODS
    Publication number: 20140235008
    Abstract: Back side illumination (BSI) sensors, manufacturing methods thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece having a front side and a back side opposite the front side. An integrated circuit is formed on the workpiece, and a first insulating material is formed on the back side of the workpiece. A second insulating material is formed over the first insulating material. The second insulating material is patterned to form a grid on the back side of the workpiece.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • WRITE ASSIST CIRCUIT, MEMORY DEVICE AND METHOD
    Publication number: 20140233330
    Abstract: A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
  • PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140225222
    Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Chemical Dispense System with Reduced Contamination
    Publication number: 20140224334
    Abstract: An apparatus includes a production tool and a pipe connected to the production tool. The pipe includes an inner pipe formed of a metal-free material, an outer pipe encircling the inner pipe, and an inlet connected to a channel between the inner pipe and the outer pipe. The apparatus further includes a chemical supply system connected to the pipe. The chemical supply system is configured to supply a chemical through a channel encircled by the inner pipe to the production tool.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Double Channel Doping in Transistor Formation
    Publication number: 20140227846
    Abstract: A method includes performing a first well doping on a first active region and a second active region simultaneously, and forming a first and a second dummy gate covering a first middle portion of the first active region and a second middle portion of the second active region, respectively. The first and the second dummy gates are removed, and the second middle portion of the second active region is covered with a mask. A second well doping is performed on the first middle portion when the mask is on the second middle portion. After the second well doping, a first gate dielectric and a first gate electrode are formed on the first middle portion to form a first transistor, and a second gate dielectric and a second gate electrode are formed on the second middle portion to form a second transistor.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 14, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Methods of Forming a Magnetic Tunnel Junction Device
    Publication number: 20140227801
    Abstract: Embodiments of the present disclosure are a method of forming a magnetic tunnel junction (MTJ) device and methods of forming a magnetic random access memory (MRAM) device. An embodiment is a method of forming a magnetic tunnel junction (MTJ) device, the method comprising forming an MTJ layer over a bottom electrode, forming a top electrode layer over the MTJ layer, and selectively etching the top electrode layer to form a top electrode over the MTJ layer. The method further comprises patterning an upper portion of the MTJ layer with an ion beam etch (IBE) process.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 14, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • FinFETs with Reduced Parasitic Capacitance and Methods of Forming the Same
    Publication number: 20140225219
    Abstract: An integrated circuit structure includes a semiconductor substrate, a semiconductor strip over a portion of the semiconductor substrate, and a Shallow Trench Isolation (STI) region on a side of the semiconductor strip. The STI region includes a dielectric layer, which includes a sidewall portion on a sidewall of the semiconductor strip and a bottom portion. The dielectric layer has a first etching rate when etched using a diluted HF solution. The STI region further includes a dielectric region over the bottom portion of the dielectric layer. The dielectric region has an edge contacting an edge of the sidewall portion of the dielectric layer. The dielectric region has a second etching rate when etched using the diluted HF solution, wherein the second etching rate is smaller than the first etching rate.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 14, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Groove Design for Retaining Ring
    Publication number: 20140224766
    Abstract: An embodiment includes an annular ring having an intended direction of rotation, the ring having a top side and a bottom side, and further having an outer perimeter and an inner perimeter, and a multitude of grooves in the bottom side of the ring, each groove having an entry point at the outer perimeter connected to an exit point at the inner perimeter creating an opening through the ring, and each groove oriented so that an angle of each groove is obtuse, wherein the angle of each groove is defined as an angle between a first ray having an initial point at the entry point and having a direction along the groove towards the exit point, and a second ray having an initial point at the entry point and having a direction tangent to the annular ring at the entry point and opposite the intended direction of rotation.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 14, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Method and System for Image-Based Defect Alignment
    Publication number: 20140226893
    Abstract: The present disclosure provides one embodiment of a method for defect diagnosis to a semiconductor wafer. The method includes collecting raw data that include a defect image (IMG), defect coordinate-on-wafer (CW) and layout database (DB); performing an image-based defect alignment to IMG according to CW and DB; and compensating coordinate mismatch according to the image-based defect alignment.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.