Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.

Abstract: The present disclosure is related to a thin film transistor. The thin film transistor may include a gate pattern; an active layer pattern; a gate insulating layer between the gate pattern and the active layer pattern; a first conductive pattern including a first pattern part and a first connecting part; a second conductive pattern a second pattern part and a second connecting part; and a first intermediate insulating layer between the first pattern part and the second pattern part. The first conductive pattern and the second conductive pattern may be a source pattern and a drain pattern, respectively. A first through hole may be provided on the first intermediate insulating layer. The second conductive pattern may be connected to the active layer pattern through the second connecting part in the first through hole.

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.