Abstract: Aspects of the disclosed technology include a method including extracting, by a processor, a plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the layout and the netlist of the circuit; computing, by the processor, respective lifetime distributions of the plurality of extracted features based on at least one circuit profile; and estimating, by the processor, a lifetime of the circuit by combining the respective lifetime distributions of the plurality of extracted features.

Abstract: Methods and systems have been proposed to estimate the remaining lifetime of an electronic integrated circuit that incorporates error-correcting code memory by using the failed memory bits as an indicator for the remaining lifetime of the circuit. The number of failed memory bits correlates with the remaining lifetime of the circuit, but varies as a function of wearout mechanism and use conditions. The methodology incorporates algorithms and test patterns to diagnose the cause of memory cell failure. By linking the failed bits to the wearout mechanism and by using lifetime simulation, the remaining lifetime of the circuit is estimated.

Abstract: Aspects of the disclosed technology include a method including extracting, by a processor, a plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the layout and the netlist of the circuit; computing, by the processor, respective lifetime distributions of the plurality of extracted features based on at least one circuit profile; and estimating, by the processor, a lifetime of the circuit by combining the respective lifetime distributions of the plurality of extracted features.

Abstract: Methods and systems have been proposed to estimate the remaining lifetime of an electronic integrated circuit that incorporates error-correcting code memory by using the failed memory bits as an indicator for the remaining lifetime of the circuit. The number of failed memory bits correlates with the remaining lifetime of the circuit, but varies as a function of wearout mechanism and use conditions. The methodology incorporates algorithms and test patterns to diagnose the cause of memory cell failure. By linking the failed bits to the wearout mechanism and by using lifetime simulation, the remaining lifetime of the circuit is estimated.