Abstract: A liquid flow path portion of a vapor chamber according to the present invention includes a plurality of main flow grooves which each extend in the first direction and through which working fluid in liquid form passes. A convex array which includes a plurality of liquid flow path convex portions arranged in the first direction via a communicating groove, is provided between a pair of the main flow grooves adjacent to each other. Each of the communicating grooves allows communication between the corresponding pair of the main flow grooves. The width of the communicating groove is larger than the width of the main flow groove.

Abstract: A liquid flow path portion of a vapor chamber according to the present invention includes a plurality of main flow grooves which each extend in the first direction and through which working fluid in liquid form passes. A convex array which includes a plurality of liquid flow path convex portions arranged in the first direction via a communicating groove, is provided between a pair of the main flow grooves adjacent to each other. Each of the communicating grooves allows communication between the corresponding pair of the main flow grooves. The width of the communicating groove is larger than the width of the main flow groove.

Abstract: A liquid flow path portion of a vapor chamber according to this invention includes a first main flow groove, a second main flow groove and a third main flow groove. A first convex array including a plurality of first convex portions arranged via a first communicating groove is provided between the first main flow groove and the second main flow groove. A second convex array including a plurality of second convex portions arranged via a second communicating groove is provided between the second main flow groove and the third main flow groove. The main flow groove includes a first intersection at which at least a part of the first communicating groove faces each second convex portion and a second intersection at which at least a part of the second communicating groove faces each first convex portion.

Abstract: A liquid flow path portion of a vapor chamber according to this invention includes a first main flow groove, a second main flow groove and a third main flow groove. A first convex array including a plurality of first convex portions arranged via a first communicating groove is provided between the first main flow groove and the second main flow groove. A second convex array including a plurality of second convex portions arranged via a second communicating groove is provided between the second main flow groove and the third main flow groove. The main flow groove includes a first intersection at which at least a part of the first communicating groove faces each second convex portion and a second intersection at which at least a part of the second communicating groove faces each first convex portion.

Abstract: A liquid flow path portion of a vapor chamber according to this invention includes a first main flow groove, a second main flow groove and a third main flow groove. A first convex array including a plurality of first convex portions arranged via a first communicating groove is provided between the first main flow groove and the second main flow groove. A second convex array including a plurality of second convex portions arranged via a second communicating groove is provided between the second main flow groove and the third main flow groove. The main flow groove includes a first intersection at which at least a part of the first communicating groove faces each second convex portion and a second intersection at which at least a part of the second communicating groove faces each first convex portion.

Abstract: A liquid flow path portion of a vapor chamber according to this invention includes a first main flow groove, a second main flow groove and a third main flow groove. A first convex array including a plurality of first convex portions arranged via a first communicating groove is provided between the first main flow groove and the second main flow groove. A second convex array including a plurality of second convex portions arranged via a second communicating groove is provided between the second main flow groove and the third main flow groove. The main flow groove includes a first intersection at which at least a part of the first communicating groove faces each second convex portion and a second intersection at which at least a part of the second communicating groove faces each first convex portion.

Abstract: A liquid flow path portion of a vapor chamber according to this invention includes a first main flow groove, a second main flow groove and a third main flow groove. A first convex array including a plurality of first convex portions arranged via a first communicating groove is provided between the first main flow groove and the second main flow groove. A second convex array including a plurality of second convex portions arranged via a second communicating groove is provided between the second main flow groove and the third main flow groove. The main flow groove includes a first intersection at which at least a part of the first communicating groove faces each second convex portion and a second intersection at which at least a part of the second communicating groove faces each first convex portion.

Abstract: A liquid flow path portion of a vapor chamber according to the present invention includes a plurality of main flow grooves which each extend in the first direction and through which working fluid in liquid form passes. A convex array which includes a plurality of liquid flow path convex portions arranged in the first direction via a communicating groove, is provided between a pair of the main flow grooves adjacent to each other. Each of the communicating grooves allows communication between the corresponding pair of the main flow grooves. The width of the communicating groove is larger than the width of the main flow groove.

Abstract: A liquid flow path portion of a vapor chamber according to this invention includes a first main flow groove, a second main flow groove and a third main flow groove. A first convex array including a plurality of first convex portions arranged via a first communicating groove is provided between the first main flow groove and the second main flow groove. A second convex array including a plurality of second convex portions arranged via a second communicating groove is provided between the second main flow groove and the third main flow groove. The main flow groove includes a first intersection at which at least a part of the first communicating groove faces each second convex portion and a second intersection at which at least a part of the second communicating groove faces each first convex portion.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.

Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.

Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.

Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.