Patents by Inventor Taizo Yasuda

Taizo Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296167
    Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Kenichi Kusumoto, Taizo Yasuda, Hidekazu Nobuto, Kohei Morita
  • Patent number: 11043414
    Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Taizo Yasuda, Hidekazu Nobuto, Kohei Morita
  • Publication number: 20210118676
    Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Kenichi Kusumoto, Taizo Yasuda, Hidekazu Nobuto, Kohei Morita
  • Publication number: 20110265595
    Abstract: A pair of wiring structures 9 and 9 configured to transmit a control signal from an operating switch on an upper portion of a shift lever 3 to a vehicle body side respectively include connection terminals 91 to be attached to a framework portion of a knob 4. Each connection terminal 91 includes: a connecting portion 93 on an end of the connection terminal 91, the connecting portion 93 being connectable to an opponent terminal; a hook portion 95 to which an end portion 90a of a lead wire 90 is to be fixed, the hook portion 95 located on another end of the connection terminal 91; and an insertion portion 92 and a position regulating portion 94 between the connecting portion 93 and the hook portion 95, the insertion portion 92 being inserted into an insertion hole in a bracket 50, the position regulating portion 94 being configured to regulate a position of the insertion portion 92 in the inserting direction.
    Type: Application
    Filed: April 26, 2011
    Publication date: November 3, 2011
    Applicant: FUJI KIKO CO., LTD.
    Inventors: Norihito SHIOJI, Taizo YASUDA
  • Publication number: 20110260288
    Abstract: Provided is a method for manufacturing a semiconductor device comprising: a process of forming a first trench 101 in insulating material layer 100 formed on a semiconductor substrate, wherein the first trench has an upper width W2 larger than an lower width W1, and is extended in a first direction; a process of forming embedded layer 102 within the first trench 101, wherein the embedded layer has a height lower than the top of the trench; a process of forming side-walls 103 to cover wall surfaces of the first trench 101 exposed on embedded layer 102; and a process of etching embedded layer 102 using side-wall 103 as a mask to separate the embedded layer in the first direction.
    Type: Application
    Filed: April 20, 2011
    Publication date: October 27, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Mitsunari Sukekawa, Taizo Yasuda
  • Publication number: 20100151685
    Abstract: A method of removing a multi-layered structure includes the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a multi-layered structure including a first film over the semiconductor substrate, a second film on the first film, and a mask pattern film on the second film. Then, the mask pattern film is removed. Then, the second film is removed by etching the second film with a first etching selectivity of the second film to the first film. The first etching selectivity is greater than a second etching selectivity of the second film to the first film with which the second film is patterned by etching using the mask pattern film. Then, the third film is removed.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 17, 2010
    Applicant: Elpida Memory, Inc.
    Inventor: Taizo YASUDA
  • Patent number: 7566654
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming an interconnection layer including a top tungsten layer, forming a mask pattern on the tungsten layer, nitriding a portion of the tungsten layer in a plasma nitriding process to form a tungsten nitride layer, etching the tungsten nitride layer while leaving the mask pattern on the tungsten layer, and patterning the interconnection layer by using the mask pattern as an etching mask.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: July 28, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Taizo Yasuda
  • Publication number: 20080090409
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming an interconnection layer including a top tungsten layer, forming a mask pattern on the tungsten layer, nitriding a portion of the tungsten layer in a plasma nitriding process to form a tungsten nitride layer, etching the tungsten nitride layer while leaving the mask pattern on the tungsten layer, and patterning the interconnection layer by using the mask pattern as an etching mask.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 17, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Taizo YASUDA