Patents by Inventor Taizoh Sadoh

Taizoh Sadoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a plurality of different functional elements and method of manufacturing the same
    Patent number: 8963124
    Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masanobu Miyao, Hiroshi Nakashima, Taizoh Sadoh, Ichiro Mizushima, Masaki Yoshimaru
  • Method for manufacturing semiconductor wafer including a strained silicon layer
    Patent number: 7767548
    Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: August 3, 2010
    Assignees: Sumco Corporation, Kyushu University, National University Corporation
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao, Taizoh Sadoh
  • SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF DIFFERENT FUNCTIONAL ELEMENTS AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20090236587
    Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.
    Type: Application
    Filed: March 17, 2009
    Publication date: September 24, 2009
    Inventors: Masanobu MIYAO, Hiroshi Nakashima, Taizoh Sadoh, Ichiro Mizushima, Masaki Yoshimaru
  • Method for Manufacturing Semiconductor Wafer
    Publication number: 20090047526
    Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.
    Type: Application
    Filed: August 17, 2007
    Publication date: February 19, 2009
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao, Taizoh Sadoh