Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: The processor includes the first through third areas which can be initialized based on an input of the PRST signal. The second and third areas can be initialized based on an input of the HRST signal. The third area can be initialized based on an input of the SRST signal. The first area is not initialized if the second reset signal is generated. The first and second areas are not initialized if the third reset signal is generated. When initialization is to performed, the values of the flags corresponding to each area are referred to. Only those areas whose values of the flags have been reset are initialized.

Abstract: The present invention provides a data processor including an instruction cache that can operate at low power consumption, avoiding useless power consumption. The data processor includes a plurality of cache memory units, wherein only a cache memory unit that stores a demanded instruction is enabled, while other memory units are disabled.

Abstract: In a semiconductor integrated circuit device, a first circuit has a clock generating circuit which generates a clock signal. A second circuit receives the clock signal from the clock generating circuit. The first circuit maintains the clock signal at a fixed frequency when an operating clock frequency of the first circuit is changed to another frequency. The first circuit supplies a control signal and the clock signal to the second circuit so that an operating clock frequency of the second circuit is determined based on a combination of the control signal and the clock signal.

Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: The processor includes the first through third areas which can be initialized based on an input of the PRST signal. The second and third areas can be initialized based on an input of the HRST signal. The third area can be initialized based on an input of the SRST signal. The first area is not initialized if the second reset signal is generated. The first and second areas are not initialized if the third reset signal is generated. When initialization is to performed, the values of the flags corresponding to each area are referred to. Only those areas whose values of the flags have been reset are initialized.

Abstract: In a semiconductor integrated circuit device, a first circuit has a clock generating circuit which generates a clock signal. A second circuit receives the clock signal from the clock generating circuit. The first circuit maintains the clock signal at a fixed frequency when an operating clock frequency of the first circuit is changed to another frequency. The first circuit supplies a control signal and the clock signal to the second circuit so that an operating clock frequency of the second circuit is determined based on a combination of the control signal and the clock signal.

Abstract: An information processing device for efficiently processing the VLIW instructions is disclosed. The information processing device includes an m×n (m-row×n-column) instruction buffer, a plurality of instruction executing parts executing a plurality of instructions in parallel, and a control circuit for selecting a predetermined number of instructions from the m×n instruction buffer and distributing the instructions to the instruction executing parts.

Abstract: The present invention provides a data processor including an instruction cache that can operate at low power consumption, avoiding useless power consumption. The data processor includes a plurality of cache memory units, wherein only a cache memory unit that stores a demanded instruction is enabled, while other memory units are disabled.