Abstract: A method of operating on encrypted data can be performed by receiving ciphertexts at a server that is configured to operate on the ciphertexts generated using a 3rd generation RGSW based fully homomorphic encryption system, operating on the ciphertexts received at the server in response to requested operations to generate respective input ciphertexts including ciphertext polynomials and ciphertext integers that are representative of the input ciphertexts, and processing the input ciphertexts in a server processing-in-memory device, that is operatively coupled to the server, to perform operations on the input ciphertext using the server processing-in-memory device, in-situ.

Abstract: A method of searching for a query sequence of nucleotide characters within a chromosomal or genomic nucleic acid reference sequence can include receiving a query sequence representing nucleotide characters to be searched for within a reference sequence of characters represented by a reference hypervector generated by combining respective base hypervectors for each nucleotide character included in the reference sequence of characters appearing in all sub-strings of characters having a length between a specified lower length and a specified upper length within the reference sequence, combining respective near orthogonal base hypervectors for each of the nucleotide characters included in the query sequence to generate a query hypervector, and generating a dot product of the query hypervector and the reference hypervector to determine a decision score indicating a degree to which the query sequence is included in the reference sequence.

Abstract: A hyperdimensional processing system can be configured to process hyperdimensional (HD) data, where the system can include a CPU configured to receive compiled binary executable data including CPU native instructions and hyperdimensional processing unit (HPU) native instructions, wherein the CPU is configured to store the CPU native instructions in a main memory coupled to the CPU for retrieval and execution by the CPU, the CPU further configured to forward the HPU native instructions to a HPU. The HPU can be configured to receive HPU native instructions native instructions and to store the HPU native instructions in a hyperdimensional memory coupled to the HPU for retrieval and execution by the CPU. Other aspects and embodiments according to the present invention are also disclosed herein.

Abstract: A method of providing a trained machine learning model can include providing a trained non-binary hyperdimensional machine learning model that includes a plurality of trained hypervector classes, wherein each of the trained hypervector classes includes N elements, and then, eliminating selected ones of the N elements from the trained non-binary hyperdimensional machine learning model based on whether the selected element has a similarity with other ones of the N elements, to provide a sparsified trained non-binary hyperdimensional machine learning model.

Abstract: An electronic device includes multiple communication interfaces and a processor coupled to the interfaces. The processor is operable to identify an interface that can transfer data with a performance of a parameter that is closer to a desired performance level than the performance of the same parameter by another interface, and is operable to transfer the data via the identified interface. Such a device can, without operator input, select and transfer data via the communication interface that gives the best data-transfer performance relative to a particular parameter such as power consumption. Furthermore, if the performance of the selected communication interface changes during the data transfer, the device may, without operator input, identify an interface that offers better performance and switch over to transferring the data transfer via the identified interface. Moreover, the device may, without operator input, allow a number of software applications to share a lesser number of interfaces.

Abstract: A method controls the operation of devices which communicate over a wireless communications channel. The method includes determining a parameter of a received signal communicated over the wireless communications channel and determining a minimum threshold value of the received signal. An average duration of fade is determined using the parameter and the minimum threshold. The method detects whether the received signal is less than the minimum threshold value. At least one of the devices is placed in a sleep mode for approximately the average duration of fade in response to the received signal being detected as less than the minimum threshold value. The determined parameter of the received signal may be the root mean square value of the received signal.

Abstract: An electronic device includes multiple communication interfaces and a processor coupled to the interfaces. The processor is operable to identify an interface that can transfer data with a performance of a parameter that is closer to a desired performance level than the performance of the same parameter by another interface, and is operable to transfer the data via the identified interface. Such a device can, without operator input, select and transfer data via the communication interface that gives the best data-transfer performance relative to a particular parameter such as power consumption. Furthermore, if the performance of the selected communication interface changes during the data transfer, the device may, without operator input, identify an interface that offers better performance and switch over to transferring the data transfer via the identified interface. Moreover, the device may, without operator input, allow a number of software applications to share a lesser number of interfaces.

Abstract: A method and device for testing and manufacturing integrated circuits such as microprocessors, memories, ASICs, programmable logic, and other types of integrated circuits. A test system is designed to test the relevant integrated circuit. A device under test emulator responds to the test system. If modifications are needed, the test system can be modified, and used to test actual devices.

Abstract: A method and device for testing and manufacturing integrated circuits such as microprocessors, memories, ASICs, programmable logic, and other types of integrated circuits. A test system is designed to test the relevant integrated circuit. A device under test emulator responds to the test system. If modifications are needed, the test system can be modified, and used to test actual devices.