Abstract: Method for forming a wiring in a semiconductor device having a cell array region and a peripheral region, which allows to form a micron pattern below a critical resolution of an exposure, including the steps of (1) forming a conduction layer and a sacrificial wiring layer on a substrate in succession, (2) selectively removing the sacrificial wiring layer to form a virtual wiring line having a sloped end portion, (3) forming sidewall insulating films at sides of the virtual wiring line excluding the sloped end portion, (4) removing the virtual wiring line entirely, (5) forming a mask layer on regions of the pad and peri region pads and other wirings are to be formed thereon, and (6) using the mask layer and the sidewalls in removing the conduction layer selectively, to form a micron pattern.

Abstract: A method for fabricating a semiconductor device and an isolation structure thereof is disclosed. The isolation structure of a semiconductor device includes a first isolation step for forming a line-shaped active region on a semiconductor substrate wherein the line-shaped active region is consecutive in a lengthy direction, and a second isolation step for electrically isolating the line-shaped active regions in a lengthy direction by a predetermined length for thereby overcoming the problems such as a rounded corner portion problem, a pattern length decrease, etc. and enhancing the integrity of the semiconductor device.