Patents by Inventor Tak-kwong Ng
Tak-kwong Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9354880Abstract: A processing device for high-speed execution of a computer program is provided. A memory module may store one or more computer programs. A sequencer may select one of the computer programs and controls execution of the selected program. A register module may store intermediate values associated with a current calculation set, a set of output values associated with a previous calculation set, and a set of input values associated with a subsequent calculation set. An external interface may receive the set of input values from a computing device and provides the set of output values to the computing device. A computation interface may provide a set of operands for computation during processing of the current calculation set. The set of input values are loaded into the register and the set of output values are unloaded from the register in parallel with processing of the current calculation set.Type: GrantFiled: March 11, 2013Date of Patent: May 31, 2016Assignee: THE UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATIONInventors: Tak-Kwong Ng, Carl S. Mills
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Patent number: 8473663Abstract: A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.Type: GrantFiled: January 21, 2011Date of Patent: June 25, 2013Assignee: United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Kevin M. Somervill, Tak-kwong Ng, Wilfredo Torres-Pomales, Mahyar R. Malekpour
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Publication number: 20110213910Abstract: A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.Type: ApplicationFiled: January 21, 2011Publication date: September 1, 2011Applicant: USA as represented by the Administrator of the National Aeronautics and Space Adm.Inventors: Kevin M. Somervill, Tak-kwong Ng, Wilfredo Torres-Pomales, Mayhar R. Malekpour
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Patent number: 7647543Abstract: An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.Type: GrantFiled: September 27, 2006Date of Patent: January 12, 2010Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Tak-kwong Ng, Jeffrey A. Herath
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Patent number: 7590904Abstract: An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.Type: GrantFiled: September 14, 2006Date of Patent: September 15, 2009Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Tak-Kwong Ng, Jeffrey A. Herath
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Publication number: 20070198892Abstract: An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.Type: ApplicationFiled: September 14, 2006Publication date: August 23, 2007Applicant: U.S.A. as represented by the Administrator of National Aeronautics and Space AdministrationInventors: Tak-Kwong Ng, Herath A. Jeffrey
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Publication number: 20070176627Abstract: An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.Type: ApplicationFiled: September 27, 2006Publication date: August 2, 2007Applicants: and Space AdministrationInventors: Tak-kwong Ng, Jeffrey A. Herath
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Patent number: 7107203Abstract: A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.Type: GrantFiled: September 6, 2000Date of Patent: September 12, 2006Assignee: Quickturn Design Systems Inc.Inventors: William F. Beausoleil, R. Bryan Cook, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, Lawrence A. Thomas, Norton J. Tomassetti
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Patent number: 7089538Abstract: A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cycle, the memory controller disables the main data memories on the module, and allows the maintenance bus to read or write data to these memories.Type: GrantFiled: September 6, 2000Date of Patent: August 8, 2006Assignee: Quicktum Design Systems, Inc.Inventors: William F. Beausoleil, R. Bryan Cook, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, Lawrence A. Thomas, Norton J. Tomassetti
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Patent number: 7047179Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.Type: GrantFiled: June 11, 2003Date of Patent: May 16, 2006Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, N. James Tomassetti
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Patent number: 7043417Abstract: In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.Type: GrantFiled: September 6, 2000Date of Patent: May 9, 2006Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, R. Bryan Cook, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, Lawrence A. Thomas, Norton J. Tomassetti
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Patent number: 6901359Abstract: A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.Type: GrantFiled: September 6, 2000Date of Patent: May 31, 2005Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, R. Bryan Cook, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, Lawrence A. Thomas, Norton J. Tomassetti
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Patent number: 6850880Abstract: A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.Type: GrantFiled: September 6, 2000Date of Patent: February 1, 2005Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, R. Bryan Cook, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, Lawrence A. Thomas, Norton J. Tomassetti
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Publication number: 20030212539Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.Type: ApplicationFiled: June 11, 2003Publication date: November 13, 2003Applicant: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, Tak-Kwong Ng, Helmut Roth, Peter Tannenbaum, N. James Tomassetti
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Patent number: 6618698Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.Type: GrantFiled: August 12, 1999Date of Patent: September 9, 2003Assignee: Quickturn Design Systems, Inc.Inventors: William F. Beausoleil, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, N. James Tomassetti
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Patent number: 6491205Abstract: Chips requiring high temperature reflow for attachment to a module substrate are attached first and then a eutectic water soluble solder paste and/or water soluble flux is dispensed on both the TSOP and the PBGA chip pads instead of using the paste screening techniques. The dispensing is done by injecting solder on the solder sites individually. Characteristics of the solder paste used is that it must be fluid enough to be injected onto the individual sites yet have enough body that it remains in place and does not run from site to site once dispensed. A paste capable of providing such characteristics is one having: a ) a very fine particle size in the range of 400 to 500 mesh and preferably between 400 and 450 mesh; b) a low viscosity (below 500 k centerpoise and preferably between 425 to 375 cps); and c) a solid content of 86% or lower and preferably between 84 and 80%.Type: GrantFiled: September 21, 2001Date of Patent: December 10, 2002Assignee: International Business Machines CorporationInventors: Chon C. Lei, Jac A. Burke, William F. Beausoleil, N. James Tomassetti, Lawrence A. Thomas, Tak-kwong Ng, Michael Kessler
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Patent number: 6051030Abstract: Emulation modules containing an increased number of emulation processors are logically reconfigured into a plurality of planes which are interconnected by means of multiplexors to avoid I/O pinout complexities introduced by the increase in the number of emulation processors. The emulation processors present on an emulation module chip or board are partitioned into a plurality N of different planes or arrays which are interconnected with one another and with off-chip or off-board components via N-way multiplexors. One set of multiplexors provides an input function for each of the planes. Another N-way multiplexor provides output functionality for these same set of planes. An output driver for off-board or chip communication is connected to an N-way output multiplexor. Likewise, an input receiver receives input from off-chip or off-board sources and supplies this signal to all of the N-way multiplexors which provide input signals to the various arrays of emulation processors.Type: GrantFiled: March 31, 1998Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventors: William F. Beausoleil, Tak-Kwong Ng
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Patent number: 6035117Abstract: In an emulation system, the emulation processors are grouped in clusters which are capable of interchanging information between both input memory stacks and data memory stacks associated with each of the processor elements. This capability significantly enhances the performance of emulation engines and, in particular, it provides a mechanism for emulation of memory array elements in computer systems in a more efficient and faster manner.Type: GrantFiled: March 31, 1998Date of Patent: March 7, 2000Assignee: International Business Machines CorporationInventors: William F. Beausoleil, Roy G. Musselman, Tak-Kwong Ng, Helmut Roth
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Patent number: 5551013Abstract: A software-driven multiprocessor emulation system comprising a plurality of emulation processors connected in parallel in a module. One or more modules of processors comprise an emulation system. An execution unit in each processor includes a table-lookup unit for emulating any type of logic gate function. A parallel bus connects an output of each processor to a multiplexor input with every other processor in a module. Each processor embeds a control store to store software logic-representing signals for controlling operations of each processor. Also a data store is embedded in each processor to receive data generated under control of the software signals in the control store. The parallel processors on each module have a module input and a module output from each processor. The plurality of modules have their module outputs inter-connected to module inputs of all other modules. A sequencer synchronously cycles the processors through mini-cycles on all modules.Type: GrantFiled: June 3, 1994Date of Patent: August 27, 1996Assignee: International Business Machines CorporationInventors: William F. Beausoleil, Tak-Kwong Ng, Harold R. Palmer
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Patent number: 5109496Abstract: A least recently used associative map is described for translating virtual memory addresses to real memory addresses. The map includes a stack of storage devices each with a comparator. The storage devices are arranged in a push down stack with an input storage device to receive the incoming virtual address and store the corresponding real address and the other storage devices coupled to the output of the previous higher storage devices and with storage devices storing the translation of virtual address and real address in order of recent use with the last or bottom storage device storing the least recently used device. When the comparator detects a compare that real address is provided out and that translation is applied to the input storage device as the most recently used translation and the other translations are shifted down the stack to replace in the storage device that had the compare with the translation from the previous storage device.Type: GrantFiled: September 27, 1989Date of Patent: April 28, 1992Assignee: International Business Machines CorporationInventors: William F. Beausoleil, Tak-Kwong Ng