Abstract: According to an aspect of the invention, there is provided a circuit board assembly including a first circuit board including a first circuit pattern formed on a surface of the first circuit board, and an opening that is adjacent to the first circuit pattern; and a second circuit board including a second circuit pattern corresponding to the first circuit pattern and a protection film that is applied to a surface of the second circuit board so as to form a hollow place located corresponding to the opening, wherein the first circuit board and the second circuit board are combined with each other.

Abstract: According to an aspect of the invention, there is provided a circuit board assembly including a first circuit board including a first circuit pattern formed on a surface of the first circuit board, and an opening that is adjacent to the first circuit pattern; and a second circuit board including a second circuit pattern corresponding to the first circuit pattern and a protection film that is applied to a surface of the second circuit board so as to form a hollow place located corresponding to the opening, wherein the first circuit board and the second circuit board are combined with each other.

Abstract: An apparatus and method for reducing power consumption in a digital image processor are disclosed. The apparatus includes a global positioning system (GPS) module using power and configured to generate initial GPS location information of the digital image processor; and a digital signal processor (DSP) configured to receive the initial GPS location information, to set user selected location information for recording in a captured image, and to cut the power to the GPS module. The method includes supplying power to a global positioning system (GPS) module; receiving initial GPS location information of the digital image processor, wherein the initial GPS location is generated by the GPS module; setting a user selected location information to capture an image; and cutting the power to the GPS module.