Abstract: A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

Abstract: A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

Abstract: A data separator produces a reference clock from encoded data through the use of a digital logic that simulates the operation of an analog phase-locked loop. The digital phase-locked loop includes a counter oscillator that develops a period value which is incrementally modified in accordance with time variations in the new input data to maintain the regenerated data in proper phase relationship with the clock. The counter oscillator includes a zero-crossing counter which produces a reference clock signal to a clock and data regeneration circuit. The counter is incremented until its count is equal to the previously computed normal period value. This counter value is latched by a syncronized input data and represents the required period adjustment. As the data is syncronized with the reference clock the value of this adjustment approaches zero.