Patents by Inventor Tak Yee Kwan

Tak Yee Kwan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7737701
    Abstract: A method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate is disclosed. The method includes generating a step signal on one of the at least one signal path connected to a respective contact, and capturing a capacitively coupled signal due to the step signal at the contact. The method further includes determining the integrity of the electrical connection from a characteristic of the capacitively coupled signal or a response signal obtained from the capacitively coupled signal. A tester in which the method is implemented is also disclosed.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: June 15, 2010
    Assignee: Agilent Technologies, Inc.
    Inventors: Eddie L Williamson, Tak Yee Kwan
  • Publication number: 20090079440
    Abstract: A method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate is disclosed. The method includes generating a step signal on one of the at least one signal path connected to a respective contact, and capturing a capacitively coupled signal due to the step signal at the contact. The method further includes determining the integrity of the electrical connection from a characteristic of the capacitively coupled signal or a response signal obtained from the capacitively coupled signal. A tester in which the method is implemented is also disclosed.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Eddie L Williamson, Tak Yee Kwan
  • Patent number: 7307427
    Abstract: A method and apparatus is presented for gaining socket testability through the use of a capacitive interposer engineered to create capacitive coupling between signal nodes of a circuit assembly that the tester has access to and nodes of the socket that would not otherwise have any coupling to a testable signal node of the socket. Generally, coupling capacitance is engineered into the interposer by trace and via routing between the signal node of the socket and a location in close proximity to the inaccessible socket node such that their proximity to each other couples them together.
    Type: Grant
    Filed: July 23, 2005
    Date of Patent: December 11, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Chris R. Jacobsen, Kenneth P. Parker, Myron J. Schneider, Tak Yee Kwan