Patents by Inventor Taka Inoue

Taka Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9316516
    Abstract: A magnetic excitation circuit is used as a circuit for providing a magnetic excitation electric current based on a magnetic excitation power supply voltage to a magnetic excitation coil of an electromagnetic flow meter. The magnetic excitation circuit includes four voltage storing circuits that store and output a driving voltage that is charged by a common driving voltage. The voltage storing circuits are connected respectively between the control terminals and the output terminals of four switching elements. When the four switching elements are turned ON in relation to a positive interval or a negative interval, the four switching elements operate by the driving voltages that are outputted from the respective voltage storing circuits.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: April 19, 2016
    Assignee: AZBIL CORPORATION
    Inventors: Osamu Momose, Ichiro Mitsutake, Shinsuke Matsunaga, Taka Inoue, Masahide Ushiyama
  • Patent number: 9112455
    Abstract: In a signal amplifying circuit, a flow rate signal, inputted between flow rate signal input terminals of a connector, is inputted into one input terminal and the other input terminal of an instrumentation amplifier through resistive elements and subjected to differential amplification. The amplified output signal thereof is outputted to a sample hold circuit through a coupling capacitor. The flow rate signals, inputted between the flow rate signal input terminals, are buffered by buffer amplifiers, and output signals thereof are outputted to a fault detecting circuit. An interconnection, which connects one of the flow rate signal input terminals and a non-inverting input terminal of one of the buffer amplifiers, is guarded by a guard ring pattern. An interconnection, which connects the other one of the flow rate signal input terminals and a non-inverting input terminal of the other one of the buffer amplifiers, is guarded by another guard ring pattern.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: August 18, 2015
    Assignee: AZBIL CORPORATION
    Inventors: Osamu Momose, Ichiro Mitsutake, Shinsuke Matsunaga, Taka Inoue, Masahide Ushiyama
  • Publication number: 20140266438
    Abstract: In a signal amplifying circuit, a flow rate signal, inputted between flow rate signal input terminals of a connector, is inputted into one input terminal and the other input terminal of an instrumentation amplifier through resistive elements and subjected to differential amplification. The amplified output signal thereof is outputted to a sample hold circuit through a coupling capacitor. The flow rate signals, inputted between the flow rate signal input terminals, are buffered by buffer amplifiers, and output signals thereof are outputted to a fault detecting circuit. An interconnection, which connects one of the flow rate signal input terminals and a non-inverting input terminal of one of the buffer amplifiers, is guarded by a guard ring pattern. An interconnection, which connects the other one of the flow rate signal input terminals and a non-inverting input terminal of the other one of the buffer amplifiers, is guarded by another guard ring pattern.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 18, 2014
    Applicant: AZBIL CORPORATION
    Inventors: Osamu MOMOSE, Ichiro MITSUTAKE, Shinsuke MATSUNAGA, Taka INOUE, Masahide USHIYAMA
  • Publication number: 20140247532
    Abstract: A magnetic excitation circuit is used as a circuit for providing a magnetic excitation electric current based on a magnetic excitation power supply voltage to a magnetic excitation coil of an electromagnetic flow meter. The magnetic excitation circuit includes four voltage storing circuits that store and output a driving voltage that is charged by a common driving voltage. The voltage storing circuits are connected respectively between the control terminals and the output terminals of four switching elements. When the four switching elements are turned ON in relation to a positive interval or a negative interval, the four switching elements operate by the driving voltages that are outputted from the respective voltage storing circuits.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 4, 2014
    Applicant: Azbil Corporation
    Inventors: Osamu MOMOSE, Ichiro MITSUTAKE, Shinsuke MATSUNAGA, Taka INOUE, Masahide USHIYAMA
  • Patent number: 8571816
    Abstract: Gain switching is performed by a DC amplifying circuit. The DC amplifying circuit is provided with individual gain generating circuits and a gain selecting circuit, and saturation preventing circuits are provided in earlier stages than the individual gain generating circuits. The individual gain generating circuit generates a gain G1, the individual gain generating circuit generates a gain G2 (where G2>G1), and the individual gain generating circuit generates a gain G3 (where G3>G2). The gain selecting circuit selects, as a used gain generating circuit, one of the individual gain generating circuits, and sends the output thereof to an A/D converting circuit in a later stage.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: October 29, 2013
    Assignee: Azbil Corporation
    Inventors: Taka Inoue, Ichirou Mitsutake
  • Publication number: 20110264382
    Abstract: Gain switching is performed by a DC amplifying circuit. The DC amplifying circuit is provided with individual gain generating circuits and a gain selecting circuit, and saturation preventing circuits are provided in earlier stages than the individual gain generating circuits. The individual gain generating circuit generates a gain G1, the individual gain generating circuit generates a gain G2 (where G2>G1), and the individual gain generating circuit generates a gain G3 (where G3>G2). The gain selecting circuit selects, as a used gain generating circuit, one of the individual gain generating circuits, and sends the output thereof to an A/D converting circuit in a later stage.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 27, 2011
    Applicant: YAMATAKE CORPORATION
    Inventors: Taka Inoue, Ichirou Mitsutake
  • Patent number: 7950292
    Abstract: In a constant current circuit, a constant current is caused to flow through a resistor, thereby causing a constant voltage to occur across the resistor. This constant voltage is then superimposed on an output signal of an operational amplifier that is to be fed back to the drain of a field effect transistor, thereby maintaining the same potential in an AC manner between the output terminal of the operational amplifier and the drain of the field effect transistor. In this way, the gate and drain of the field effect transistor is caused to exhibit the same potential in an AC manner, so that no current will occur through the stray capacitance between the gate and drain of the field effect transistor. As a result, similarly to a case of using a feedback capacitor, the input impedance of the field effect transistor can be raised.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: May 31, 2011
    Assignee: Yamatake Corp.
    Inventors: Yutaka Harada, Ichiro Mitsutake, Kouji Okuda, Taka Inoue, Tetsuya Kajita
  • Publication number: 20100071476
    Abstract: In a constant current circuit, a constant current is caused to flow through a resistor, thereby causing a constant voltage to occur across the resistor. This constant voltage is then superimposed on an output signal of an operational amplifier that is to be fed back to the drain of a field effect transistor, thereby maintaining the same potential in an AC manner between the output terminal of the operational amplifier and the drain of the field effect transistor. In this way, the gate and drain of the field effect transistor is caused to exhibit the same potential in an AC manner, so that no current will occur through the stray capacitance between the gate and drain of the field effect transistor. As a result, similarly to a case of using a feedback capacitor, the input impedance of the field effect transistor can be raised.
    Type: Application
    Filed: August 3, 2007
    Publication date: March 25, 2010
    Applicant: Yamatake Corporation
    Inventors: Yutaka Harada, Ichiro Mitsutake, Kouji Okuda, Taka Inoue, Tetsuya Kajita