Abstract: A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.

Abstract: According to one aspect of the present invention, the flash memory comprises a memory region divided into a plurality of real banks, wherein from among the plurality of products which consists of a plurality of combinations of virtual banks having at least one real bank; and a combination of the top boot in which the most significant address is allocated to the boot bank having the boot sector and the bottom boot in which the least significant address is allocated to the boot bank, product information data are set in a product information record section, whereby any product can be configured.

Abstract: A semiconductor memory, such as an SDRAM, includes a data bus pair, a first reset circuit, a second reset circuit and a control circuit. The first reset circuit is connected between the buses of the data bus pair and resets the buses at a first potential. The second reset circuit is also connected between the data buses and resets the buses at a second potential. The control circuit is connected to the first and second reset circuits and activates the first reset circuit and deactivates the second reset circuit prior to a write operation. The control circuit further deactivates the first reset circuit and activates the second reset circuit prior to a read operation.

Abstract: A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.

Abstract: A semiconductor memory device includes a control circuit that sets read and write latency periods such that the write data input circuit is activated and acquires the write data after the receipt of a write command and upon the lapse of the write latency period. The write latency period of the memory device is set to be one latency value less than the read latency period.

Abstract: A semiconductor memory, such as an SDRAM, includes a data bus pair, a first reset circuit, a second reset circuit and a control circuit. The first reset circuit is connected between the buses of the data bus pair and resets the buses at a first potential. The second reset circuit is also connected between the data buses and resets the buses at a second potential. The control circuit is connected to the first and second reset circuits and activates the first reset circuit and deactivates the second reset circuit prior to a write operation. The control circuit further deactivates the first reset circuit and activates the second reset circuit prior to a read operation.

Abstract: A semiconductor memory, such as an SDRAM, includes a data bus pair, a first reset circuit, a second reset circuit and a control circuit. The first reset circuit is connected between the buses of the data bus pair and resets the buses at a first potential. The second reset circuit is also connected between the data buses and resets the buses at a second potential. The control circuit is connected to the first and second reset circuits and activates the first reset circuit and deactivates the second reset circuit prior to a write operation. The control circuit further deactivates the first reset circuit and activates the second reset circuit prior to a read operation.

Abstract: A direct sensing type semiconductor memory device combines read and write data bus lines in order to conserve real estate. The memory device includes a bit line pair and a sense amplifier connected between the lines of the bit line pair, and a data line pair. A first transistor is connected between a first potential and one of the data lines of the data line pair, and a gate of the first transistor is connected to one of the bit lines of the bit line pair. A second transistor is connected between the first potential and the other one of the data lines, and its gate is connected to the other of the bit lines. A switch circuit is connected between the data line pair and the bit line pair and transfers data from the data line pair to the bit line pair in accordance with a potential difference between the data line pair and the bit line pair.

Abstract: A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: A semiconductor memory device, such as a DRAM, includes a word line multi-selection circuit. A row decoder generates a word line selecting signal for selecting a read-out word line for use in the current cycle to read information from a selected memory cell. The word line selecting signal is also used to select a write-back word line which was used in the previous cycle to read cell information and is used in the current cycle to write back cell information. The word line multi-selection circuit includes a register for temporarily storing the cell information read from the selected memory cell and also for providing, in the current cycle, information read in the previous cycle in order to perform the write-back operation.

Abstract: A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: A semiconductor memory device is operable in an operation mode selected from a read mode, a normal write mode and a block write mode. The memory device includes a memory cell array having a plurality of pairs of bit lines, a plurality of word lines and a plurality of memory cells provided at intersections of the bit lines and the word lines, wherein each pair of the bit lines and the memory cells associated with each bit line pair form one of a plurality of columns defined in the memory cell array. The memory device also includes a pair of data lines and a column selection controller, wherein the column selection controller is supplied with a group of column selection signals for selectively connecting and disconnecting the pair of data lines to and from the plurality of pairs of bit lines.

Abstract: A voltage level detector insusceptible to noise is disclosed. The voltage level detector includes a detector section, an output circuit section coupled to the detector section, and a delay circuit section provided between the detector section and the output circuit section. The detector section receives a target signal, and determines if the voltage level of the target signal lies within a predetermined voltage zone. The output circuit section outputs a detection signal when the target signal is found to be in the predetermined zone by the detector section. When the detector section detects that the target signal has come off the predetermined voltage zone, the delay circuit section delays the vanishing of the detection signal output from the output circuit section by a given delay time.

Abstract: A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: A dynamic random access memory includes a dummy word line which has an electrical characteristic identical to that of an actual word line. The dummy word line is charged up and is then discharged as in case of the actual word line. A latched row address in a row address latch circuit is reset when the potential of the dummy word line becomes equal to a predetermined low potential due to the discharge operation for the dummy word line.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of word lines; a row pre-decoding unit responsive to a row address signal, outputting a plurality of row pre-decode signals with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of the row address signal; a row pre-decode wiring for transmitting the plurality of row pre-decode signals; a row main decoder responsive to one signal in each group of the plurality of row pre-decode signals, carrying out a main decoding for selecting one of the plurality of word lines; a pseudo row decoder having substantially same electrical characteristics as the row main decoder, carrying out a simulation of the main decoding in response to the plurality of row pre-decode signals output on row pre-decode wiring; and a word line driver for driving a word line selected by the row main decoder to a predetermined level.